Digital Filter Structures
What we have learnt so far is how to design either an IIR or FIR digital filter to satisfy a given set of specifications in the frequency domain. We have also seen examples based on MATLAB wherein filtering operations are carried out by specific functions. We really don’t know how these functions really work. If you are a S/W or H/W engineer and want to implement a digital filter in software or hardware, you should be able to describe the flow of signal from the input to the output. Thus, a digital filter structure describes the flow of signal as it propagates from the input to the output sample by sample. This filtering operation is described by a signal flow graph, which is a block diagram with blocks corresponding to the arithmetic operations of addition, multiplication, and unit delays. The blocks are connected by lines with arrows pointing in the direction of signal flow. In digital filter terminology, an adder has two inputs and one output, as shown in Fig. 8.1a. Similarly, a multiplier accepts an input signal and multiplies it by a coefficient a to produce an output, as shown in Fig. 8.1b. A unit delay block is a register, which can hold a sample from its input. The sample can be read from its output after one sample interval. Figure 8.1c illustrates a unit delay element. Note that the unit delay operation in the Z-domain is denoted by z−1. Finally, Fig. 8.1d shows how a signal is tapped into. So, these are the basic building blocks of a digital filter structure. Let us look at a simple example.
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