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Reconfigurable Silicon Photonic Interconnect for Many-Core Architecture

  • Hang GuanEmail author
  • Sébastien Rumley
  • Ke Wen
  • David Donofrio
  • John Shalf
  • Keren Bergman
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10524)

Abstract

In the context of declining Moore and Dennard Laws, efficient utilization of chip area and transistor is more than ever required. The portion of transistors devoted to compute operations can be maximized by off-loading as much as possible data-storage onto memory chips. This, however, requires wide off-chip IO bandwidth, and furthermore increases Network-on-chip (NoC) traffic. In this paper, we first present a concept of optically connected memory modules, delivering enough bandwidth to allow for cache reduction and memory externalization. Second, we show that connecting these memory modules in a reconfigurable interconnect permit to substantially offload NoC traffic.

Keywords

Silicon photonic Multiprocessor interconnection 

Notes

Acknowledgments

This work was supported by the ASCR Office in the DOE Office of Science under contract number DE-AC02-05CH11231, and the DARPA Microsystems Technology Office (MTO) under the PERFECT (Power Efficiency Revolution for Embedded Computing Technologies) program.

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Copyright information

© Springer International Publishing AG 2017

Authors and Affiliations

  • Hang Guan
    • 1
    Email author
  • Sébastien Rumley
    • 1
  • Ke Wen
    • 1
  • David Donofrio
    • 2
  • John Shalf
    • 2
  • Keren Bergman
    • 1
  1. 1.Department of Electrical EngineeringColumbia UniversityNew YorkUSA
  2. 2.Lawrence Berkeley LabBerkeleyUSA

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