Advertisement

Robust Hybrid TFET-MOSFET Circuits in Presence of Process Variations and Soft Errors

  • Maedeh Hemmat
  • Mehdi KamalEmail author
  • Ali Afzali-Kusha
  • Massoud Pedram
Conference paper
Part of the IFIP Advances in Information and Communication Technology book series (IFIPAICT, volume 508)

Abstract

In this work, to improve the timing yield of Tunnel Field Effect Transistor (TFET) circuits in the presence of process variations as well as their soft-error resiliency, we propose replacing some of TFET-based gates by MOSFET-based ones. The effectiveness of the proposed TFET-MOSFET hybrid implementation of the circuits are investigated by first studying the impacts of the process variation on the performances (I-V characteristics) of both homojunction InAs TFETs and MOSFETs. Next, to analyze the soft error rate of the circuits, the particle hit-induced transient current profiles of these devices are extracted. Based on these studies, a hybrid TFET-MOSFET circuit design approach which improves the reliability and soft-error resiliency compared to those of pure TFET-based circuits is suggested. Finally, the efficacy of the design approach is investigated by applying it to some circuits of ISCAS’89 benchmark package.

Keywords

Tunnel FET Reliability issues Process variation Low power design Hybrid TFET-MOSFET designs Soft error 

References

  1. 1.
    Mukundrajan, R., Cotter, M., Saripalli, V., Irwin, M., Datta, S., Narayanan, V.: Ultra low power circuit design using Tunnel FETs. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 153–158. IEEE Press, MA (2012)Google Scholar
  2. 2.
    Kim, M.S., Liu, H., Swaminathan, K., Li, X., Datta, S., Narayanan, V.: Enabling power-efficient designs with III-V tunnel FETs. In: IEEE Compound Semiconductor Integrated Circuit Symposium (CSICs), pp. 1–4. IEEE Press, California (2014)Google Scholar
  3. 3.
    Chen, Y.-N., Fan, M.-L., Hu, V.-H., Su, P., Chuang, C.-T.: Evaluation of stability, performance of ultra-low voltage MOSFET, TFET, and mixed TFET-MOSFET SRAM cell with write-assist circuits. J. Emerg. Sel. Top. Circuits Syst. 4, 389–399 (2014)CrossRefGoogle Scholar
  4. 4.
    Migita, S., Matsukawa, T., Mori, T., Fukuda, K., Morita, Y., Mizubayashi, W.: Variation behavior of tunnel-FETs originated from dopant concentration at source region and channel edge configuration. In: 44th European Solid State Device Research Conference (ESSDERC), pp. 278–281. IEEE Press, Venice (2014)Google Scholar
  5. 5.
    Zhang, L., Chan, M., He, F.: The impact of device parameter variation on double gate tunneling FET and double gate MOSFET. In: IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC), pp. 1–4. IEEE Press, Hong Kong (2010)Google Scholar
  6. 6.
    Damrongplasit, N., Shin, C., Kim, S.H., Vega, R.A., Liu, T.-J.K.: Study of random dopant fluctuation effects in germanium-source tunnel FETs. J. Electron Devices. 58, 3541–3548 (2011)CrossRefGoogle Scholar
  7. 7.
    Hemmat, M., Kamal, M., Afzali-Kusha, A., Pedram, M.: Study on the impact of device parameter variations on performance of III-V homojunction and heterojunction tunnel FETs. J. Solid State Electron. 124, 46–53 (2016)CrossRefGoogle Scholar
  8. 8.
    Hemmat, M., Kamal, M., Afzali-Kusha, A., Pedram, M.: Hybrid TFET-MOSFET circuits: an approach to design reliable ultra-low power circuits in the presence of process variation. In: IEEE International conference on Very Large Scale Integration (VLSI-SoC), pp. 1–6. IEEE Press, Tallinn (2016)Google Scholar
  9. 9.
    Dhillon, Y.S., Diril, A.U., Chatterjee, A.: Soft-error tolerance analysis and optimization of nanometer circuits. In: IEEE International conference on Design, Automation, and Test in Europe, pp. 389–400. Springer, GA (2008)Google Scholar
  10. 10.
    Liu, H., Cotter, M., Datta, S., Narayanan, V. : Technology assessment of Si and III-V FinFETs and III-V tunnel FETs from soft error rate perspective. In: IEEE International Electron Devices Meeting (IEDM), pp. 25.5.1–25.5.4. IEEE Press, California (2012)Google Scholar
  11. 11.
    Datta, S., Liu, H., Narayanan, V.: Tunnel FET technology: a reliability perspective. J. Microelectron. Reliab. 54, 861–874 (2014)CrossRefGoogle Scholar
  12. 12.
    Hemmat, M., Kamal, M., Afzali-Kusha, A., Pedram, M.: Hybrid TFET-MOSFET circuit: a solution to design soft-error resilient ultra-low power digital circuit. J. Integr. VLSI J. 57, 11–19 (2017)CrossRefGoogle Scholar
  13. 13.
    Tura, A.: Novel Vertical Tunnel Transistors for Continued Voltage Scaling. Ph.D. dissertation, Univ. of California, Los Angeles (2010)Google Scholar
  14. 14.
    Mishra, A., Jha, K.K., Pattanaik, M.: Parameter variation aware hybrid TFET-CMOS based power gating technique with a temperature variation tolerant sleep mode. J. Microelectron. 45, 1515–1521 (2014)CrossRefGoogle Scholar
  15. 15.
    Liu, H., Datta, S.: III-V Tunnel FET model manual. The Pennsylvania state university (2015)Google Scholar
  16. 16.
    Cotter, M., Liu, H., Datta, S., Narayanan, V.: Evaluation of tunnel FET-based flip-flop designs for low power, high performance applications. In: 14th International Symposium on Quality Electronic Design (ISQED), pp. 430–437. IEEE Press, California (2013)Google Scholar
  17. 17.
    Miskov-Zivanov, N., Marculescu, D.: Modeling and optimization for soft-error reliability of sequential circuits. J. Comput. Aided Design Integr. Circuits Syst. 27, 803–816 (2008)Google Scholar
  18. 18.
    Lin, S., Kim, Y.-B., Lombardi, F.: Soft-error hardening designs of nanoscale CMOS latches. In: 27th IEEE Symposium on VLSI Test, pp. 41–46. IEEE Press, Washington (2009)Google Scholar

Copyright information

© IFIP International Federation for Information Processing 2017

Authors and Affiliations

  • Maedeh Hemmat
    • 1
  • Mehdi Kamal
    • 1
    Email author
  • Ali Afzali-Kusha
    • 1
  • Massoud Pedram
    • 2
  1. 1.School of Electrical and Computer EngineeringUniversity of TehranTehranIran
  2. 2.Department of Electrical EngineeringUniversity of Southern CaliforniaLos AngelesUSA

Personalised recommendations