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Novel Bypass Attack and BDD-based Tradeoff Analysis Against All Known Logic Locking Attacks

  • Xiaolin XuEmail author
  • Bicky Shakya
  • Mark M. Tehranipoor
  • Domenic Forte
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10529)

Abstract

Logic locking has emerged as a promising technique for protecting gate-level semiconductor intellectual property. However, recent work has shown that such gate-level locking techniques are vulnerable to Boolean satisfiability (SAT) attacks. In order to thwart such attacks, several SAT-resistant logic locking techniques have been proposed, which minimize the discriminating ability of input patterns to rule out incorrect keys. In this work, we show that such SAT-resistant logic locking techniques have their own set of unique vulnerabilities. In particular, we propose a novel “bypass attack” that ensures the locked circuit works even when an incorrect key is applied. Such a technique makes it possible for an adversary to be oblivious to the type of SAT-resistant protection applied on the circuit, and still be able to restore the circuit to its correct functionality. We show that such a bypass attack is feasible on a wide range of benchmarks and SAT-resistant techniques, while incurring minimal run-time and area/delay overhead. Binary decision diagrams (BDDs) are utilized to analyze the proposed bypass attack and assess tradeoffs in security vs overhead of various countermeasures.

Notes

Acknowledgment

This research is supported in part by Cisco Systems Inc, and by the AFOSR award number FA9550-14-1-0351.

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Copyright information

© International Association for Cryptologic Research 2017

Authors and Affiliations

  • Xiaolin Xu
    • 1
    Email author
  • Bicky Shakya
    • 1
  • Mark M. Tehranipoor
    • 1
  • Domenic Forte
    • 1
  1. 1.ECE DepartmentUniversity of FloridaGainesvilleUSA

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