A Concurrency Control Protocol that Selects Accessible Replicated Pages to Avoid Latch Collisions for B-Trees in Manycore Environments

Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10439)


In recent years, microprocessor vendors aiming for dramatic performance improvement have introduced manycore processors with over 100 cores on a single chip. To take advantage of this in database and storage systems, it is necessary for B-trees and their concurrency control to reduce the number of latch collisions and interactions among the cores. Concurrency control methods such as physiological partitioning (PLP), which assigns cores to partitions in a value–range partition, have been studied. These methods perform effectively for nearly static and uniform workloads using multicore processors. However, their performance deteriorates significantly if there is major restructuring of B-trees against skew and for changing workloads. The manycore approach has a high likelihood of causing workload skew, given the lower power of each core, with an accompanying severe degradation in performance. This issue is critical for database and storage systems, which demand consistent high performance even against dynamic workloads. To address this problem, we propose an efficient new concurrency control method suitable for manycore processor platforms, called the selecting accessible replicated pages (SARP) B-tree concurrency control method. SARP achieves a consistent high performance with robustness against workload skew by distributing the workload to many cores on manycore processors, while reducing latch collisions and interactions among the cores. By applying parallel B-trees to shared-everything environments, SARP selects execution cores and access paths that distribute workloads widely to cores with appropriate processor characteristics. Experimental results using a Linux server with an Intel Xeon Phi manycore processor demonstrated that the proposed system could achieve a throughput of 44 times that for PLP in the maximum-skew case and could maintain the throughput at 66% of a throughput for uniform workloads.


  1. 1.
    Intel 64 and ia-32 architectures optimization reference manual. http://www.intel.com/content/dam/doc/manual/64-ia-32-architectures-optimization-manual.pdf
  2. 2.
    Intel 64 and ia-32 architectures software developers manual. http://download.intel.com/design/processor/manuals/253668.pdf
  3. 3.
    Apache: Hadoop. http://hadoop.apache.org/
  4. 4.
    Cha, S.K., Hwang, S., Kim, K., Kwon, K.: Cache-conscious concurrency control of main-memory indexes on shared-memory multiprocessor systems. In: Proceedings of VLDB 2001, pp. 181–190 (2001)Google Scholar
  5. 5.
    Graefe, G.: Write-optimized B-trees. In: Proceedings of VLDB 2004, pp. 672–683 (2004)Google Scholar
  6. 6.
    Graefe, G., Kimura, H., Kuno, H.A.: Foster b-trees. ACM Trans. Database Syst. 37(3), 17 (2012)CrossRefGoogle Scholar
  7. 7.
    Gray, J., Reuter, A.: Transaction Processing: Concepts and Techniques. Morgan Kaufmann, San Mateo (1992)MATHGoogle Scholar
  8. 8.
    Jeffers, J., Reinders, J.: Intel Xeon Phi Coprocessor High Performance Programming, 1st edn. Morgan Kaufmann, San Francisco (2013)Google Scholar
  9. 9.
    Jeffers, J., Reinders, J., Sodani, A.: Intel Xeon Phi Processor High Performance Programming, 2nd edn. Morgan Kaufmann, San Francisco (2016)Google Scholar
  10. 10.
    Johnson, T., Shasha, D.: Utilization of B-trees with inserts, deletes and modifies. In: Proceedings of PODS 1989, pp. 235–246 (1989)Google Scholar
  11. 11.
    Jung, H., Han, H., Fekete, A.D., Heiser, G., Yeom, H.Y.: A scalable lock manager for multicores. In: Proceedings of ACM SIGMOD 2013, pp. 73–84 (2013)Google Scholar
  12. 12.
    Karnagel, T., Dementiev, R., Rajwar, R., Lai, K., Legler, T., Schlegel, B., Lehner, W.: Improving in-memory database index performance with intel\(^{\textregistered }\) transactional synchronization extensions. In: Proceedings of HPCA 2014, pp. 476–487 (2014)Google Scholar
  13. 13.
    Kimura, H.: FOEDUS: OLTP engine for a thousand cores and NVRAM. In: Proceedings of ACM SIGMOD 2015, pp. 691–706 (2015)Google Scholar
  14. 14.
    Kissinger, T., Schlegel, B., Habich, D., Lehner, W.: KISS-Tree: smart latch-free in-memory indexing on modern architectures. In: Proceedings of DaMoN 2012, pp. 16–23 (2012)Google Scholar
  15. 15.
    Leis, V., Kemper, A., Neumann, T.: Exploiting hardware transactional memory in main-memory databases. In: Proceedings of ICDE 2014, pp. 580–591 (2014)Google Scholar
  16. 16.
    Levandoski, J.J., Lomet, D.B., Sengupta, S.: The bw-tree: a b-tree for new hardware platforms. In: Proceedings of ICDE 2013, pp. 302–313 (2013)Google Scholar
  17. 17.
    Love, R.: Linux J. 2003(111), 8 (2003)Google Scholar
  18. 18.
    Mao, Y., Kohler, E., Morris, R.T.: Cache craftiness for fast multicore key-value storage. In: Proceedings of EuroSys 2012, pp. 183–196 (2012)Google Scholar
  19. 19.
    Pandis, I., Tözün, P., Johnson, R., Ailamaki, A.: PLP: page latch-free shared-everything OLTP. PVLDB 4(10), 610–621 (2011)Google Scholar
  20. 20.
    Porobic, D., Liarou, E., Tözün, P., Ailamaki, A.: Atrapos: adaptive transaction processing on hardware islands. In: Proceedings of ICDE 2014, pp. 688–699 (2014)Google Scholar
  21. 21.
    Sewall, J., Chhugani, J., Kim, C., Satish, N., Dubey, P.: PALM: parallel architecture-friendly latch-free modifications to B+ trees on many-core processors. PVLDB 4(11), 795–806 (2011)Google Scholar
  22. 22.
    Tu, S., Zheng, W., Kohler, E., Liskov, B., Madden, S.: Speedy transactions in multicore in-memory databases. In: Proceedings of ACM SIGOPS 2013, pp. 18–32 (2013)Google Scholar
  23. 23.
    Yokota, H., Kanemasa, Y., Miyazaki, J.: Fat-Btree: an update-conscious parallel directory structure. In: Proceedings of ICDE 1999, pp. 448–457 (1999)Google Scholar
  24. 24.
    Yoshihara, T., Dai, K., Yokota, H.: A concurrency control protocol for parallel b-tree structures without latch-coupling for explosively growing digital content. In: Proceedings of EDBT 2008, pp. 133–144 (2008)Google Scholar

Copyright information

© Springer International Publishing AG 2017

Authors and Affiliations

  1. 1.Research and Development GroupHitachi, Ltd.KanagawaJapan
  2. 2.Department of Computer ScienceTokyo Institute of TechnologyTokyoJapan

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