Conclusions

Abstract

This book has proposed gain-cell embedded DRAM (GC-eDRAM) as a promising alternative to SRAM for the implementation of embedded memories in low-power VLSI SoCs. The presented GC-eDRAM circuits were targeted at a broad range of low-power VLSI SoCs, from ultra-low power systems operated at subthreshold (sub-V_T) voltages to power-aware high-performance systems operated at near-threshold (near-V_T) or nominal supply voltages. It was shown that the key to achieve energy efficiency in GC-eDRAM is a proper understanding and control of the factors that determine the data retention time and its statistical distribution.