Parameter Sensitivity in Virtual FPGA Architectures

  • Peter FiguliEmail author
  • Weiqiao Ding
  • Shalina Figuli
  • Kostas Siozios
  • Dimitrios Soudris
  • Jürgen Becker
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10216)


Virtual FPGAs add the benefits of increased flexibility and application portability on bitstream level across any underlying commercial off-the-shelf FPGAs at the expense of additional area and delay overhead. Hence it becomes a priority to tune the architecture parameters of the virtual layer. Thereby, the adoption of parameter recommendations intended for physical FPGAs can be misleading, as they are based on transistor level models. This paper presents an extensive study of architectural parameters and their effects on area and performance by introducing an extended parameterizable virtual FPGA architecture and deriving suitable area and delay models. Furthermore, a design space exploration methodology based on these models is carried out. An analysis of over 1400 benchmark-runs with various combinations of cluster and LUT size reveals high parameter sensitivity with variances up to \(\pm 95.9\%\) in area and \(\pm 78.1\%\) in performance and a discrepancy to the studies on physical FPGAs.


FPGA Virtualization Cluster size LUT size Efficiency 



This work was partially supported by the German Academic Exchange Service (DAAD).


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Copyright information

© Springer International Publishing AG 2017

Authors and Affiliations

  • Peter Figuli
    • 1
    Email author
  • Weiqiao Ding
    • 1
  • Shalina Figuli
    • 1
  • Kostas Siozios
    • 2
  • Dimitrios Soudris
    • 3
  • Jürgen Becker
    • 1
  1. 1.Institute for Information Processing TechnologyKarlsruhe Institute of TechnologyKarlsruheGermany
  2. 2.Department of PhysicsAristotle University of ThessalonikiThessalonikiGreece
  3. 3.School of Electrical and Computer EngineeringNational Technical University of AthensAthensGreece

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