Hardware-Accelerated Radix-Tree Based String Sorting for Big Data Applications

  • Christopher Blochwitz
  • Julian Wolff
  • Jan Moritz Joseph
  • Stefan Werner
  • Dennis Heinrich
  • Sven Groppe
  • Thilo Pionteck
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10172)

Abstract

In this paper, a scalable hardware architecture for string sorting in the application field of Big Data is presented. Current hardware architectures focus on the acceleration of sorting small sets of data with a maximum string length. In contrast, we propose an FPGA-accelerated architecture based on Radix-Trees, which has the ability to sort large sets of strings without practical limitation of the string length. The Radix-Tree is parameterizable and so is the design, which enables the adaptation for application-specific properties, such as diversity of strings and size of the used alphabet. The scalable design has a hierarchical processing and memory architecture, which operate in parallel. Optimal parameters and configurations are evaluated by using a dataset of the Semantic Web, as an example of Big Data applications. The results are analyzed with a focus on throughput, memory requirement, and utilization. The hardware design is faster for all values of the radix parameter and achieves a maximum speed-up factor of 2.78 compared to a software system.

Keywords

Radix-Tree Big data Dictionary generation Semantic web String sorting Field-programmable gate array 

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Copyright information

© Springer International Publishing AG 2017

Authors and Affiliations

  • Christopher Blochwitz
    • 1
  • Julian Wolff
    • 1
  • Jan Moritz Joseph
    • 3
  • Stefan Werner
    • 2
  • Dennis Heinrich
    • 2
  • Sven Groppe
    • 2
  • Thilo Pionteck
    • 3
  1. 1.Institute of Computer EngineeringUniversität zu LübeckLübeckGermany
  2. 2.Institute of Information SystemsUniversität zu LübeckLübeckGermany
  3. 3.Hardware-Oriented Technical Computer ScienceUniversität MagdeburgMagdeburgGermany

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