A Petri Net Design and Verification Platform Based on The Scalable and Parallel Architecture: HiPS

Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 558)

Abstract

This paper proposes an on-the-fly linear temporal logic model checker using state-space generation based on Petri net models. The hierarchical Petri net simulator (HiPS) tool, developed by our research group at Shinshu University, is a design and verification environment for Place/Transition nets and is capable of generating state-space and trace-process graphs. In combination with external tools, HiPS can perform exhaustive model checking for a state space. However, exhaustive model checking is required for generating a complete state space. On-the-fly model checking is an approach for solving the explosion problem to generate a portion of the overall state space by parallelizing the search and generation processes. In this study, we propose a model checker for a Petri net model to concurrently function with state-space generation using an interprocess communication channel. By utilizing the concept of fluency, we implement automata-based model checking for Petri nets. This implementation achieves high-efficiency for on-the-fly verification, which is independent of the verification and state-space generation processes.

Keywords

Petri net Model checking On-the-fly Linear Temporal Logic (LTL) Scalability 

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Copyright information

© Springer International Publishing AG 2018

Authors and Affiliations

  1. 1.Interdisciplinary Graduate School of Science and TechnologyShinshu UniversityNaganoJapan

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