Fast Hardware Architectures for Supersingular Isogeny Diffie-Hellman Key Exchange on FPGA

  • Brian KozielEmail author
  • Reza Azarderakhsh
  • Mehran Mozaffari-Kermani
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10095)


In this paper, we present a constant-time hardware implementation that achieves new speed records for the supersingular isogeny Diffie-Hellman (SIDH), even when compared to highly optimized Haswell computer architectures. We employ inversion-free projective isogeny formulas presented by Costello et al. at CRYPTO 2016 on an FPGA. Modern FPGA’s can take advantage of heavily parallelized arithmetic in \(\mathbb {F}_{p^{2}}\), which lies at the foundation of supersingular isogeny arithmetic. Further, by utilizing many arithmetic units, we parallelize isogeny evaluations to accelerate the computations of large-degree isogenies by approximately 57%. On a constant-time implementation of 124-bit quantum security SIDH on a Virtex-7, we generate ephemeral public keys in 10.6 and 11.6 ms and generate the shared secret key in 9.5 and 10.8 ms for Alice and Bob, respectively. This improves upon the previous best time in the literature for 768-bit implementations by a factor of 1.48. Our 83-bit quantum security implementation improves upon the only other implementation in the literature by a speedup of 1.74 featuring fewer resources and constant-time.


Post-quantum cryptography Elliptic curve cryptography Isogeny-based cryptography Field programmable gate array 



This material is based upon work supported by the NSF CNS-1464118 and NIST 60NANB16D246 grants awarded to Reza Azarderakhsh.


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Copyright information

© Springer International Publishing AG 2016

Authors and Affiliations

  • Brian Koziel
    • 1
    Email author
  • Reza Azarderakhsh
    • 2
  • Mehran Mozaffari-Kermani
    • 3
  1. 1.Texas InstrumentsDallasUSA
  2. 2.CEECS DepartmentI-SENSE FAUBoca RatonUSA
  3. 3.EME DepartmentRITRochesterUSA

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