HW/SW Co-design Toolset for Customization of Exposed Datapath Processors

  • Pekka Jääskeläinen
  • Timo Viitanen
  • Jarmo Takala
  • Heikki Berg
Chapter

Abstract

Customized processors are an interesting option for implementing software defined radios; they bring benefits of tailored fixed function hardware while adding new advantages such as reduced implementation verification effort and increased post-fabrication flexibility. To reduce the engineering costs and the time-to-market of platforms with new computing devices, the processor customization process should be supported with automated design flows that include tools like retargeting compilers, instruction-set simulators, and RTL generators. This chapter presents an open source processor co-design toolset that is based on a computation resource oriented design methodology where the primary design choices are the set of resources to include in the processor at hand, instead of focusing on instruction encoding details. The toolset is based on a retargetable high-level language compiler and a scalable exposed datapath template which support different styles of parallelism available in applications. In addition to various published academic processor design examples for SDR algorithms, the tools have been used to design and program processors that have been implemented down to silicon layout level and integrated in commercial grade chips.

References

  1. 1.
    Cilio, A., Schot, H., Janssen, J., Jääskeläinen, P.: Architecture definition file: processor architecture definition file format for a new TTA design framework (2014). http://tce.cs.tut.fi/specs/ADF.pdf Google Scholar
  2. 2.
    Corporaal, H.: Transport triggered architectures: design and evaluation. Ph.D. thesis, TU Delft (1995)Google Scholar
  3. 3.
    Corporaal, H.: Microprocessor Architectures: From VLIW to TTA. Wiley, Chichester (1997)Google Scholar
  4. 4.
    Corporaal, H., Mulder, H.: MOVE: a framework for high-performance processor design. In: Proceedings of ACM/IEEE Conference on Supercomputing, pp. 692–701 (1991). doi:http://doi.acm.org/10.1145/125826.126159
  5. 5.
    Dally, W., Balfour, J., Black-Shaffer, D., Chen, J., Harting, R., Parikh, V., Park, J., Sheffield, D.: Efficient embedded computing. Computer 41, 27–32 (2008). doi:http://doi.ieeecomputersociety.org/10.1109/MC.2008.224
  6. 6.
    He, Y., She, D., Mesman, B., Corporaal, H.: MOVE-Pro: A low power and high code density TTA architecture. In: Proceedings of International Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), pp. 294–301 (2011). doi:10.1109/SAMOS.2011.6045474
  7. 7.
    Jääskeläinen, P., de La Lama, C., Huerta, P., Takala, J.: OpenCL-based design methodology for application-specific processors. Trans. HiPEAC 5 (2011). Available onlineGoogle Scholar
  8. 8.
    Jääskeläinen, P., Kultala, H., Viitanen, T., Takala, J.: Code density and energy efficiency of exposed datapath architectures. J. Signal Process. Syst. 1–16 (2014). doi:10.1007/s11265-014-0924-x. http://dx.doi.org/10.1007/s11265-014-0924-x
  9. 9.
    Jääskeläinen, P., de La Lama, C.S., Schnetter, E., Raiskila, K., Takala, J., Berg, H.: pocl: a performance-portable OpenCL implementation. Int. J. Parallel Prog. 1–34 (2014). doi:10.1007/s10766-014-0320-y. http://dx.doi.org/10.1007/s10766-014-0320-y
  10. 10.
    Lattner, C., Adve, V.: LLVM: a compilation framework for lifelong program analysis & transformation. In: Proceedings of the International Symposium on Code Generation Optimization, pp. 75–87 (2004)Google Scholar
  11. 11.
    Lipovski, G.: The architecture of a simple, effective control processor. In: 2nd Euromicro Symposium on Microprocessing and Microprogramming, pp. 7–19 (1976)Google Scholar
  12. 12.
    TCE: TTA-based co-design environment (2015). http://tce.cs.tut.fi
  13. 13.
    Thuresson, M., Själander, M., Björk, M., Svensson, L., Larsson-Edefors, P., Stenström, P.: FlexCore: Utilizing exposed datapath control for efficient computing. In: Proceedings of International Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), pp. 18–25 (2007). doi:10.1109/ICSAMOS.2007.4285729
  14. 14.
    Viitanen, T., Kultala, H., Jääskeläinen, P., Takala, J.: Heuristics for greedy transport triggered architecture interconnect exploration. In: Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES ’14, pp. 2:1–2:7. ACM, New York, NY (2014). doi:10.1145/2656106.2656123. http://doi.acm.org/10.1145/2656106.2656123

Copyright information

© Springer International Publishing Switzerland 2017

Authors and Affiliations

  • Pekka Jääskeläinen
    • 1
  • Timo Viitanen
    • 1
  • Jarmo Takala
    • 1
  • Heikki Berg
    • 2
  1. 1.Tampere University of TechnologyTampereFinland
  2. 2.Nokia TechnologiesTampereFinland

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