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A Distributed Formal Model for the Analysis and Verification of Arbitration Protocols on MPSoCs Architecture

  • Imen Ben Hafaiedh
  • Maroua Ben SlimaneEmail author
  • Riadh Robbana
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10048)

Abstract

In digital system design, control access protocols are used to allocate shared resources. Whenever a resource, such as a bus is shared, an arbiter is required to assign the access to the resource at a particular time. In SoC (System on Chip) architectures, the design, analysis and implementation of such arbiter, are becoming increasingly important due to their significant impact on the performance and efficiency of such systems. In this paper, we provide a high-level abstract and formal model of MPSoCs architecture. The proposed model provides a way to easily implement, analyze and compare different arbitration protocols. It also allows to study relevant properties such as fairness, mutual exclusion and deadlock freedom at a high level of abstraction. The studied protocols as well as the MPSoC architecture have been modeled in a distributed manner which makes the generation of a distributed implementation more relevant.

Keywords

Mutual Exclusion Priority Rule Dynamic Priority Equal Priority Deadlock Freedom 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer International Publishing AG 2016

Authors and Affiliations

  • Imen Ben Hafaiedh
    • 1
    • 2
  • Maroua Ben Slimane
    • 1
    • 3
    Email author
  • Riadh Robbana
    • 1
    • 4
  1. 1.FST, Laboratoire LIP2Université de Tunis El ManarTunisTunisie
  2. 2.ISIUniversité de Tunis El ManarTunisTunisie
  3. 3.EPTUniversité de CarthageLa MarsaTunisie
  4. 4.INSATUniversité de CarthageTunisTunisie

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