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Optimized Mapping Spiking Neural Networks onto Network-on-Chip

  • Yu Ji
  • Youhui ZhangEmail author
  • He Liu
  • Weimin Zheng
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10048)

Abstract

Mapping spiking neural networks (SNNs) onto network-on-chips (NoCs) is pivotal to fully utilize the hardware resources of dedicated multi-core processors (CMPs) for SNNs’ simulation. This paper presents such a mapping framework from the aspect of architecture evaluation. Under this framework, we present two strategies accordingly: The first tends to put highly communicating tasks together. The second is opposite, which aims at SNN features to achieve a balanced distribution of neurons according to their active degrees; for communication-intensive and unbalanced SNNs, this one can alleviate NoC congestion and improve the simulation speed more. This framework also contains a customized NoC simulator to evaluate mapping strategies. Results show that our strategies can achieve a higher simulation speed (up to 1.37 times), and energy consumptions can be reduced or rise very limited.

Keywords

Mapping Strategy Transmission Delay Active Degree Deep Belief Network Simulation Speed 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    National Academy of Engineering: Reverse-Engineer the Brain (2012). http://www.engineeringchallenges.org/cms/8996/9109.aspx
  2. 2.
    Jin, X.: Parallel simulation of neural networks on spinnaker universal neuromorphic hardware. Ph.D. thesis, University of Manchester (2010)Google Scholar
  3. 3.
    Paugam-Moisy, H., Bohte, S.: Computing with spiking neuron networks. In: Rozenberg, G., Bäck, T., Kok, J.N. (eds.) Handbook of Natural Computing, pp. 335–376. Springer, Heidelberg (2012)CrossRefGoogle Scholar
  4. 4.
    Merolla, P.A., Arthur, J.V., Alvarez-Icaza, R., et al.: A million spiking-neuron integrated circuit with a scalable communication network and interface. Science 345(6197), 668–673 (2014)CrossRefGoogle Scholar
  5. 5.
    Furber, S.B., Lester, D.R., Plana, L.A., Garside, J.D., Painkras, E., Temple, S., Brown, A.D.: Overview of the SpiNNaker system architecture. IEEE Trans. Comput. 62(12), 2454–2467 (2013)MathSciNetCrossRefGoogle Scholar
  6. 6.
    Benjamin, B.V., Gao, P., McQuinn, E., Choudhary, S., Chandrasekaran, A.R., Bussat, J.-M., Alvarez-Icaza, R., Arthur, J.V., Merolla, P.A., Boahen, K.: Neurogrid: a mixed-analog-digital multichip system for large-scale neural simulations. Proc. IEEE 102(5), 699–716 (2014)CrossRefGoogle Scholar
  7. 7.
  8. 8.
    Pande, S., Morgan, F., Smit, G., Bruintjes, T., Rutgers, J., McGinley, B., Cawley, S., Harkin, J., McDaid, L.: Fixed latency on-chip interconnect for hardware spiking neural network architectures. Parallel Comput. 39, 357–371 (2013)CrossRefGoogle Scholar
  9. 9.
    Seo, J.S., Brezzo, B., Liu, Y., et al.: A 45 nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. In: IEEE Custom Integrated Circuits Conference (CICC) (2011)Google Scholar
  10. 10.
    Esser, S.K., Andreopoulos, A., Appuswamy, R., Datta, P., Barch, D., Amir, A.: Cognitive computing programming paradigm: a corelet language for composing networks of neurosynaptic cores. In: The International Joint Conference on Neural Networks (2013)Google Scholar
  11. 11.
    Akopyan, F., Sawada, J., Cassidy, A., et al.: TrueNorth design and tool flow of a 65 mW 1 million neuron programmable neurosynaptic chip. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 34(10), 1537–1557 (2015)CrossRefGoogle Scholar
  12. 12.
    Gao, P., Benjamin, B.V., Boahen, K.: Dynamical system guided mapping of quantitative neuronal models onto neuromorphic hardware. IEEE Trans. Circ. Syst. 59(11), 2383–2394 (2011)MathSciNetGoogle Scholar
  13. 13.
    Eliasmith, C., Anderson, C.H.: Neural Engineering: Computation, Representation, and Dynamics in Neurobiological Systems. A Bradford Book, Cambridge (2004)Google Scholar
  14. 14.
    Davies, S., Navaridas, J., Galluppi, F., Furber, S.: Population-based routing in the SpiNNaker neuromorphic architecture. In: International Joint Conference on Neural Networks (IJCNN 2012), Brisbane, Australia, 10–15 June 2012Google Scholar
  15. 15.
    Carrillo, S., Harkin, J., McDaid, L.J., Morgan, F., Pande, S., Cawley, S., McGinley, B.: Scalable hierarchical network-on-chip architecture for spiking neural network hardware implementations. IEEE Trans. Parallel Distrib. Syst. 24(12), 2451–2461 (2013)CrossRefGoogle Scholar
  16. 16.
    Rodopoulos, D., Chatzikonstantis, G., Pantelopoulos, A., Soudris, D., De Zeeuw, C.I., Strydis, C.: Optimal mapping of inferior olive neuron simulations on the single-chip cloud computer. In: 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (2014)Google Scholar
  17. 17.
    Prezioso, M., Merrikh-Bayat, F., Hoskins, B.D., Adam, G.C., Likharev, K.K., Strukov, D.B.: Training and operation of an integrated neuromorphic network based on metal-oxide memristors. Nature 521, 61–64 (2015)CrossRefGoogle Scholar
  18. 18.
    Wendt, K., Ehrlich, M., Schüffny, R.: A graph theoretical approach for a multistep mapping software for the FACETS project. In: 2nd WSEAS International Conference on Computer Engineering and Applications (CEA 2008) (2008)Google Scholar
  19. 19.
    Pandea, S., Morgan, F., Smitb, G., Bruintjesb, T., Rutgersb, J., McGinleya, B., Cawleya, S., Harkin, J., McDaid, L.: Fixed latency on-chip interconnect for hardware spiking neural network architectures. Parallel Comput. J. (Elsevier) 39, 357–371 (2013)CrossRefGoogle Scholar
  20. 20.
    Philipp, S., Grübl, A., Meier, K., Schemmel, J.: Interconnecting VLSI spiking neural networks using isochronous connections. In: Sandoval, F., Prieto, A., Cabestany, J., Graña, M. (eds.) IWANN 2007. LNCS, vol. 4507, pp. 471–478. Springer, Heidelberg (2007). doi: 10.1007/978-3-540-73007-1_58 CrossRefGoogle Scholar
  21. 21.
    Vainbrand, D., Ginosar, R.: Scalable network-on-chip architecture for configurable neural networks. Microprocess. Microsyst. 35, 152–166 (2011)CrossRefGoogle Scholar
  22. 22.
    Zhu, D., Chen, L., Yue, S., Pedram, M.: Application mapping for express channel-based networks-on-chip. In: Proceedings of Design, Automation and Test in Europe, DATE (2014)Google Scholar
  23. 23.
    Sahu, P.K., Manna, N.S., Chattopadhyay, S.: Extending Kernighan-Lin partitioning heuristic for application mapping onto Network-on-Chip. J. Syst. Archit. 60(7), 562–578 (2014)CrossRefGoogle Scholar
  24. 24.
    Nisarg, S., Kanchan, M., Santanu, C.: An application mapping technique for butterfly-fat-tree network-on-chip. In: Proceedings of 2nd International Conference on Emerging Applications of Information Technology, EAIT, pp. 383–386 (2011)Google Scholar
  25. 25.
    Tosun, S.: Cluster-based application mapping method for Network-on-Chip. Adv. Eng. Softw. 42(10), 868–874 (2011)CrossRefGoogle Scholar
  26. 26.
    Brette, R., Rudolph, M., Carnevale, T., et al.: Simulation of networks of spiking neurons: a review of tools and strategies. J. Comput. Neurosci. 23(3), 349–398 (2007)MathSciNetCrossRefGoogle Scholar
  27. 27.
    Plesser, H.E., Eppler, J.M., Morrison, A., Diesmann, M., Gewaltig, M.-O.: Efficient parallel simulation of large-scale neuronal networks on clusters of multiprocessor computers. In: Kermarrec, A.-M., Bougé, L., Priol, T. (eds.) Euro-Par 2007. LNCS, vol. 4641, pp. 672–681. Springer, Heidelberg (2007). doi: 10.1007/978-3-540-74466-5_71 CrossRefGoogle Scholar
  28. 28.
    The Nengo Neural Simulator. http://www.nengo.ca/
  29. 29.
    Alexander, G.E., Crutcher, M.D.: Functional architecture of basal ganglia circuits: neural substrates of parallel processing. Trends Neurosci. 13(7), 266–271 (1990)CrossRefGoogle Scholar
  30. 30.
    Redgrave, P., Prescott, T.J., Gurney, K.: The basal ganglia: a vertebrate solution to the selection problem? Neuroscience 89(4), 1009–1023 (1999)CrossRefGoogle Scholar
  31. 31.
    Stewart, T.C., Bekolay, T., Eliasmith, C.: Learning to select actions with spiking neurons in the basal ganglia. Front. Neurosci. 6, 2 (2012)CrossRefGoogle Scholar
  32. 32.
    Tripp, B.P., Eliasmith, C.: Population models of temporal differentiation. Neural Comput. 22(3), 621–659 (2010)CrossRefzbMATHGoogle Scholar
  33. 33.
    Conklin, J., Eliasmith, C.: A controlled attractor network model of path integration in the rat. J. Comput. Neurosci. 18, 183–203 (2005)MathSciNetCrossRefGoogle Scholar
  34. 34.
    Mattson, T.G., Van der Wijngaart, R.F., Lehnig, T., Brett, P., Haas, W., Kennedy, P.: The 48-core SCC processor: the programmer’s view. In: Proceedings of 2010 International Conference for High Performance Computing, Networking, Storage and Analysis. New Orleans, LA (2010)Google Scholar
  35. 35.
    Wentzlaff, D., Griffin, P., Hoffmann, H., Bao, L., Edwards, B., Ramey, C., Mattina, M., Miao, C.-C., Brown III, J.F., Agarwal, A.: On-chip interconnection architecture of the tile processor. IEEE Comput. Soc. 27, 15–31 (2007)Google Scholar
  36. 36.
    Jerger, N.E., Peh, L.-S., Lipasti, M.: Virtual circuit tree multicasting: a case for on-chip hardware multicast support. In: ISCA (2008)Google Scholar
  37. 37.
    Fidalgo, P.A., Puente, V., Gregorio, J.A.: MRR: enabling fully adaptive multicast routing for CMP interconnection networks. In: HPCA (2009)Google Scholar
  38. 38.
    Rodrigo, S., Flich, J., Duato, J., Hummel, M.: Efficient unicast and multicast support for CMPs. In: MICRO, pp. 364–375 (2008)Google Scholar
  39. 39.
    Noxim - the NoC Simulator. http://noxim.sourceforge.net/
  40. 40.
    CACTI - An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model. http://www.hpl.hp.com/research/cacti/

Copyright information

© Springer International Publishing AG 2016

Authors and Affiliations

  1. 1.Department of Computer Science and TechnologyTsinghua UniversityBeijingChina
  2. 2.Technology Innovation Center at YinzhouYangtze Delta Region Institute of Tsinghua UniversityJiaxingChina
  3. 3.Center for Brain-Inspired Computing ResearchTsinghua UniversityBeijingChina

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