Scaling BDD-based Timed Verification with Simulation Reduction

  • Truong Khanh Nguyen
  • Tian Huat Tan
  • Jun Sun
  • Jiaying Li
  • Yang Liu
  • Manman Chen
  • Jin Song Dong
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10009)

Abstract

Digitization is a technique that has been widely used in real-time model checking. With the assumption of digital clocks, symbolic model checking techniques (like those based on BDDs) can be applied for real-time systems. The problem of model checking real-time systems based on digitization is that the number of tick transitions increases rapidly with the increment of clock upper bounds. In this paper, we propose to improve BDD-based verification for real-time systems using simulation reduction. We show that simulation reduction allows us to verify timed automata with large clock upper bounds and to converge faster to the fixpoint. The presented approach is applied to reachability and LTL verification for real-time systems. Finally, we compare our approach with existing tools such as Rabbit, Uppaal, and CTAV and show that our approach outperforms them and achieves a significant speedup.

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Copyright information

© Springer International Publishing AG 2016

Authors and Affiliations

  • Truong Khanh Nguyen
    • 1
  • Tian Huat Tan
    • 2
  • Jun Sun
    • 2
  • Jiaying Li
    • 2
  • Yang Liu
    • 3
  • Manman Chen
    • 2
  • Jin Song Dong
    • 4
  1. 1.AutodeskSan RafaelUSA
  2. 2.Singapore University of Technology and DesignSingaporeSingapore
  3. 3.Nanyang Technological UniversitySingaporeSingapore
  4. 4.National University of SingaporeSingaporeSingapore

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