Advertisement

Mixed-Critical Systems Design with Coarse-Grained Multi-core Interference

  • Peter Poplavko
  • Rany Kahil
  • Dario Socci
  • Saddek Bensalem
  • Marius Bozga
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9952)

Abstract

Those autonomic concurrent systems which are timing-critical and compute intensive need special resource managers in order to ensure adaptation to unexpected situations in terms of compute resources. So-called mixed-criticality managers may be required that adapt system resource usage to critical run-time situations (e.g., overheating, overload, hardware errors) by giving the highly critical subset of system functions priority over low-critical ones in emergency situations. Another challenge comes from the fact that for modern platforms – multi- and many- cores – make the scheduling problem more complicated because of their inherent parallelism and because of “parasitic” interference between the cores due to shared hardware resources (buses, FPU’s, DMA’s, etc.). In our work-in-progress design flow we provide the so-called concurrency language for expressing, at high abstraction level, new emerging custom resource management policies that can handle these challenges. We compile the application into a representation in this language and combine the result with a resource manager into a joint software design used to deploy the given system on the target platform. In this context, we discuss our work in progress on a scheduler that aims to handle the interference in mixed-critical applications by controlling it at the task level.

Keywords

Bandwidth interference Multi-core Embedded multiprocessor Mixed criticality 

References

  1. 1.
    Abdellatif, T., Combaz, J., Sifakis, J.: Model-based implementation of real-time applications. In: Proceedings of the Tenth ACM International Conference on Embedded Software, EMSOFT 2010. ACM (2010)Google Scholar
  2. 2.
    Abel, A., Benz, F., Doerfert, J., Dörr, B., Hahn, S., Haupenthal, F., Jacobs, M., Moin, A.H., Reineke, J., Schommer, B., Wilhelm, R.: Impact of resource sharing on performance and performance prediction: a survey. In: D’Argenio, P.R., Melgratti, H. (eds.) CONCUR 2013. LNCS, vol. 8052, pp. 25–43. Springer, Heidelberg (2013). doi: 10.1007/978-3-642-40184-8_3 CrossRefGoogle Scholar
  3. 3.
    Amnell, T., Fersman, E., Mokrushin, L., Pettersson, P., Yi, W.: TIMES - a tool for modelling and implementation of embedded systems. In: Katoen, J.-P., Stevens, P. (eds.) TACAS 2002. LNCS, vol. 2280, pp. 460–464. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  4. 4.
    Baruah, S.: Semantics-preserving implementation of multirate mixed-criticality synchronous programs. In: RTNS 2012, pp. 11–19. ACM (2012)Google Scholar
  5. 5.
    Baruah, S., Fohler, G.: Certification-cognizant time-triggered scheduling of mixed-criticality systems. In: RTSS 2011, pp. 3–12. IEEE (2011)Google Scholar
  6. 6.
    Bensalem, S., Bozga, M., Combaz, J., Triki, A.: Rigorous system design flow for autonomous systems. In: Margaria, T., Steffen, B. (eds.) ISoLA 2014. LNCS, vol. 8802, pp. 184–198. Springer, Heidelberg (2014). doi: 10.1007/978-3-662-45234-9_13 Google Scholar
  7. 7.
    Chaki, S., Kyle, D.: DMPL: programming and verifying distributed mixed-synchrony and mixed-critical software. Technical report, Carnegie Mellon University (2016). http://www.andrew.cmu.edu/user/schaki/misc/dmpl-extended.pdf
  8. 8.
    Cordovilla, M., Boniol, F., Forget, J., Noulard, E., Pagetti, C.: Developing critical embedded systems on multicore architectures: the Prelude-SchedMCore toolset. In: RTNS (2011)Google Scholar
  9. 9.
    de Dinechin, B.D., van Amstel, D., Poulhiès, M., Lager, G.: Time-critical computing on a single-chip massively parallel processor. In: DATE 2014. EDAA (2014)Google Scholar
  10. 10.
    Fersman, E., Krcl, P., Pettersson, P., Yi, W.: Task automata: schedulability, decidability and undecidability. Inf. Comput. 205(8), 1149–1172 (2007)MathSciNetCrossRefzbMATHGoogle Scholar
  11. 11.
    Giannopoulou, G., Poplavko, P., Socci, D., Huang, P., Stoimenov, N., Bourgos, P., Thiele, L., Bozga, M., Bensalem, S., Girbal, S., Faugere, M., Soulat, R., de Dinechin, B.D.: DOL-BIP-critical: a tool chain for rigorous design and implementation of mixed-criticality multi-core systems. Technical report 363, ETH Zurich, Laboratory TIK, April 2016Google Scholar
  12. 12.
    Hansson, A., Goossens, K., Bekooij, M., Huisken, J.: CoMPSoc: a template for composable and predictable multi-processor system on chips. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 14(1), 2 (2009)Google Scholar
  13. 13.
    Heijligers, M.: The application of genetic algorithms to high-level synthesis. Ph.D. thesis, University of Eindhoven (1996)Google Scholar
  14. 14.
    Lee, E., Messerschmitt, D.: Synchronous data flow. Proc. IEEE 75(9), 1235–1245 (1987)CrossRefGoogle Scholar
  15. 15.
    Pellizzoni, R., Bui, B.D., Caccamo, M., Sha, L.: Coscheduling of CPU and I/O transactions in cots-based embedded systems. In: RTSS 2008, pp. 221–231 (2008)Google Scholar
  16. 16.
    Perrotin, M., Conquet, E., Dissaux, P., Tsiodras, T., Hugues, J.: The TASTE toolset: turning human designed heterogeneous systems into computer built homogeneous software. In: ERTSS 2010 (2010)Google Scholar
  17. 17.
    Poplavko, P., Kahil, R., Socci, D., Bensalem, S., Bozga, M.: Mixed-critical systems design with coarse-grained multi-core interference. Technical report, TR-2016-4, Verimag (2016)Google Scholar
  18. 18.
    Poplavko, P., Socci, D., Bourgos, P., Bensalem, S., Bozga, M.: Models for deterministic execution of real-time multiprocessor applications. In: DATE 2015 (2015)Google Scholar
  19. 19.
    Shah, H., Coombes, A., Raabe, A., Huang, K., Knoll, A.: Measurement based wcet analysis for multi-core architectures. In: RTNS 2014. ACM (2014)Google Scholar
  20. 20.
    Socci, D., Poplavko, P., Bensalem, S., Bozga, M.: Modeling mixed-critical systems in real-time BIP. In: ReTiMiCs 2013 (2013)Google Scholar
  21. 21.
    Socci, D., Poplavko, P., Bensalem, S., Bozga, M.: Multiprocessor scheduling of precedence-constrained mixed-critical jobs. In: ISORC 2015, pp. 198–207. IEEE (2015)Google Scholar
  22. 22.
    Socci, D., Poplavko, P., Bensalem, S., Bozga, M.: Time-triggered mixed-critical scheduler on single- and multi-processor platforms (revised version). Technical report, TR-2015-8, Verimag (2015)Google Scholar
  23. 23.
    Socci, D., Poplavko, P., Bensalem, S., Bozga, M.: A timed-automata based middleware for time-critical multicore applications. In: Proceedings of SEUS 2015. IEEE (2015)Google Scholar
  24. 24.
    Sriram, S., Lee, E.A.: Determining the order of processor transactions in statically scheduled multiprocessors. VLSI Signal Process. 15(3), 207–220 (1997)CrossRefGoogle Scholar
  25. 25.
    Stuijk, S., Geilen, M., Theelen, B.D., Basten, T.: Scenario-aware dataflow: modeling, analysis and implementation of dynamic applications. In: SAMOS 2011. IEEE (2011)Google Scholar
  26. 26.
    Wirsing, M., Hölzl, M., Tribastone, M., Zambonelli, F.: ASCENS: engineering autonomic service-component ensembles. In: Beckert, B., Damiani, F., Boer, F.S., Bonsangue, M.M. (eds.) FMCO 2011. LNCS, vol. 7542, pp. 1–24. Springer, Heidelberg (2013). doi: 10.1007/978-3-642-35887-6_1 CrossRefGoogle Scholar
  27. 27.
    Zerzelidis, A., Wellings, A.J.: A framework for flexible scheduling in the RTSJ. ACM Trans. Embedded Comput. Syst. 10(1), Article no. 3 (2010)Google Scholar

Copyright information

© Springer International Publishing AG 2016

Authors and Affiliations

  • Peter Poplavko
    • 1
  • Rany Kahil
    • 1
  • Dario Socci
    • 1
  • Saddek Bensalem
    • 1
  • Marius Bozga
    • 1
  1. 1.Univ. Grenoble-Alpes, CNRS, VerimagGrenobleFrance

Personalised recommendations