A CMOS Unit Circuit Using Subthreshold Operation of MOSFETs for Chaotic Boltzmann Machines

  • Masatoshi Yamaguchi
  • Takashi Kato
  • Quan Wang
  • Hideyuki Suzuki
  • Hakaru Tamukoh
  • Takashi MorieEmail author
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9947)


Boltzmann machines are a useful model for deep neural networks in artificial intelligence, but in their software or hardware implementation, they require random number generation for stochastic operation, which consumes considerable computational resources and power. Chaotic Boltzmann machines (CBMs) have been proposed as a model using chaotic dynamics instead of stochastic operation. They require no random number generation, and are suitable for analog VLSI implementation. In this paper, we describe software simulation results for CBM operation, and propose a CMOS circuit of CBMs using the subthreshold operation of MOSFETs.


VLSI implementation Chaotic Boltzmann machine Subthreshold operation MOSFET 



This work was supported by JSPS KAKENHI Grant Nos. 15H01706 and 15K1211. The circuit design was supported by VLSI Design and Education Center(VDEC), the University of Tokyo in collaboration with Cadence Design Systems, Inc., and Synopsys, Inc.


  1. 1.
    Aarts, E., Korst, J.: Simulated Annealing and Boltzmann Machines: A Stochastic Approach to Combinatorial Optimization and Neural Computing. Wiley, New York (1989)zbMATHGoogle Scholar
  2. 2.
    Ackley, D.H., Hinton, G.E., Sejnowski, T.J.: A learning algorithm for Boltzmann machines. Cognitive Sci. 9, 147–169 (1985)CrossRefGoogle Scholar
  3. 3.
    Alspector, J., Allen, R.B.: A neuromorphic VLSI learning system. In: Losleben, P. (ed.) Advanced Research in VLSI: Proceedings of the 1987 Stanford Conference, pp. 313–349. MIT Press, Cambridge (1987)Google Scholar
  4. 4.
    Alspector, J., Gannet, J.W., Harber, S., Parker, M.B., Chu, R.: Generating mutiple analog noise sources from a single linear feedback shift register with neural network applications. In: IEEE Proceedings of International Symposium on Circuits and Systems (ISCAS), pp. 1058–1061 (1990)Google Scholar
  5. 5.
    Alspector, J., Gannet, J.W., Harber, S., Parker, M.B., Chu, R.: A VLSI-efficient technique for generating multiple uncorrelated noise sources and its application to stochastic neural networks. IEEE Trans. Circ. Syst. 38, 109–123 (1991)CrossRefGoogle Scholar
  6. 6.
    Arima, Y., Murasaki, M., Yamada, T., Maeda, A., Shinohara, H.: A refreshable analog VLSI neural network chip with 400 neurons and 40k synapses. IEEE J. Solid State Circ. 27, 1854–1861 (1992)CrossRefGoogle Scholar
  7. 7.
    Garda, P., Belhaire, E.: An analog chip set for multi-layered synchronous Boltzmann machines. In: International Neural Network Conference, vol. 2, pp. 568–571 (1990)Google Scholar
  8. 8.
    Hinton, G.E.: Deterministic Boltzmann learning performs steepest descent in weight-space. Neural Comput. 1, 143–150 (1989)CrossRefGoogle Scholar
  9. 9.
    Morie, T., Amemiya, Y.: Deterministic Boltzmann machine learning improved for analog LSI implementation. IEICE Trans. Electron. E76-C(7), 1167–1173 (1993)Google Scholar
  10. 10.
    Peterson, C., Anderson, J.R.: A mean field theory learning algorithm for neural networks. Complex Syst. 1, 995–1019 (1987)zbMATHGoogle Scholar
  11. 11.
    Salakhutdinov, R., Hinton, G.E.: Deep Boltzmann machines. In: Proceedings of AISTATS, pp. 448–455 (2009)Google Scholar
  12. 12.
    Schneider, C.R., Card, H.C.: Analog CMOS deterministic Boltzmann circuits. IEEE J. Solid State Circ. 28, 907–914 (1993)CrossRefGoogle Scholar
  13. 13.
    Suzuki, H.: Monte carlo simulation of classical spin models with chaotic billiards. Phys. Rev. E 88, 052144 (2013)Google Scholar
  14. 14.
    Suzuki, H., Imura, J., Horio, Y., Aihara, K.: Chaotic Boltzmann machines. Sci. Rep. 3, 1610 (2013)Google Scholar
  15. 15.
    Tomberg, J., Raittinen, H., Kaski, K.: VLSI architecture of the Boltzmann machine algorithm. In: International Neural Network Conference, vol. 2, pp. 568–571 (1990)Google Scholar

Copyright information

© Springer International Publishing AG 2016

Authors and Affiliations

  • Masatoshi Yamaguchi
    • 1
  • Takashi Kato
    • 1
  • Quan Wang
    • 1
  • Hideyuki Suzuki
    • 2
  • Hakaru Tamukoh
    • 1
  • Takashi Morie
    • 1
    Email author
  1. 1.Graduate School of Life Science and Systems EngineeringKyushu Institute of TechnologyKitakyushuJapan
  2. 2.Graduate School of Information Science and TechnologyOsaka UniversitySuitaJapan

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