Memory Analysis and Performance Modeling for HPC Applications on Embedded Hardware via Instruction Accurate Simulation

  • Alexander Ditter
  • Dominik Schoenwetter
  • Anton Kuzmin
  • Dietmar Fey
  • Vadym Aizinger
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 511)


The efficient usage and development of embedded multi- and many-core systems is an important field of research for years and decades. In the last decade, utilizing embedded and especially low-power architectures for high performance computing (HPC) applications became an important part of research. The reason for this are the constantly increasing energy costs along with an increasing awareness of energy consumption in general. As suitable low-power HPC architectures are not yet available at a larger scale, simulation of new and appropriate architectures becomes an important factor for the success of low-power systems and clusters. In order to speed up simulation, at the cost of accuracy, different levels of abstraction were introduced. Currently the class of instruction accurate simulations seems to yield the best trade-off between speed and precision, especially when simulating complex multi- and many-core systems. In this paper we present our investigations about the accuracy of the state-of-the-art instruction accurate embedded multi- and many-core simulation environment Open Virtual Platforms (OVP) in comparison to an actual embedded hardware system from Altera. Our investigations include the actual usage of the same operating system running on both, the target hardware and the simulation as well as serial and parallel software benchmarks. We analyze the current accuracy of the simulation environment with respect to a performance model, based on the execution time of the simulation and the actual embedded hardware system. Using the instruction accurate simulation technology from OVP is for the simulation of embedded/low-power HPC hardware architectures and applications. Furthermore, we point out first steps towards further possibilities for obtaining a better performance model by the use of our simple memory model.


Memory Access High Performance Computing Discontinuous Galerkin Real Hardware Many Integrate Core 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer International Publishing AG 2017

Authors and Affiliations

  • Alexander Ditter
    • 1
  • Dominik Schoenwetter
    • 1
  • Anton Kuzmin
    • 1
  • Dietmar Fey
    • 1
  • Vadym Aizinger
    • 2
  1. 1.Chair of Computer Science 3 (Computer Architecture)Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU)ErlangenGermany
  2. 2.Chair of Applied Mathematics (AM1)Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU)ErlangenGermany

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