Intra-CPU Traffic Estimation and Implications on Networks-on-Chip Research

  • Dmitri Moltchanov
  • Arkady Kluchev
  • Pavel Kustarev
  • Karolina Borunova
  • Alexey Platunov
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9870)


General purpose networks-on-chip (GP-NoC) are expected to feature tens or even hundreds of computational elements with complex communications infrastructure binding them into a connected network to achieve memory synchronization. The experience accumulated over the years in network design suggests that the knowledge of the traffic nature is mandatory for successful design of a networking technology. In this paper, based on the Intel CPU family, we describe traffic estimation techniques for modern multi-core GP-CPUs, discuss the traffic modeling procedure and highlight the implications of the traffic structure for GP-NoC research. The most important observation is that the traffic at internal interfaces appears to be random for external observer and has clearly identifiable batch structure.


Networks on chip Wireless network on chip Intra-CPU communications Traffic estimation 


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Copyright information

© Springer International Publishing AG 2016

Authors and Affiliations

  • Dmitri Moltchanov
    • 1
  • Arkady Kluchev
    • 2
  • Pavel Kustarev
    • 2
  • Karolina Borunova
    • 3
  • Alexey Platunov
    • 2
  1. 1.Department of Communications EngineeringTampere University of TechnologyTampereFinland
  2. 2.Department of Embedded SystemsITMO UniversitySt.-PetersburgRussia
  3. 3.Faculty of Infocommunications Networks and SystemSt.-Petersburg State University of TelecommunicationsSt.-PetersburgRussia

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