Intra-CPU Traffic Estimation and Implications on Networks-on-Chip Research

  • Dmitri Moltchanov
  • Arkady Kluchev
  • Pavel Kustarev
  • Karolina Borunova
  • Alexey Platunov
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9870)

Abstract

General purpose networks-on-chip (GP-NoC) are expected to feature tens or even hundreds of computational elements with complex communications infrastructure binding them into a connected network to achieve memory synchronization. The experience accumulated over the years in network design suggests that the knowledge of the traffic nature is mandatory for successful design of a networking technology. In this paper, based on the Intel CPU family, we describe traffic estimation techniques for modern multi-core GP-CPUs, discuss the traffic modeling procedure and highlight the implications of the traffic structure for GP-NoC research. The most important observation is that the traffic at internal interfaces appears to be random for external observer and has clearly identifiable batch structure.

Keywords

Networks on chip Wireless network on chip Intra-CPU communications Traffic estimation 

References

  1. 1.
    Intel: Intel Core i7-5960x processor extreme edition. Technical specifications (2015). http://ark.intel.com/products/82930/Intel-Core-i7-5960X-Processor-Extreme-Edition-20M-Cache-up-to-3_50-GHz. Accessed 07 June 2015
  2. 2.
    AMD: AMD FX Series Processors. Technical specifications (2015). http://www.amd.com/en-us/products/processors/desktop/fx. Accessed 07 June 2015
  3. 3.
    Mittal, S., Vetter, J., Li, D.: A survey of architectural approaches for managing embedded DRAM and non-volatile on-chip caches. IEEE Paral. Distrib. Comput. Syst. 26, 1524–1537 (2015)CrossRefGoogle Scholar
  4. 4.
    Davis, W., Wilson, J., Mick, S., Xu, J., Hua, H., Mineo, C., Sule, A., Steer, M., Franzon, P.: Demystifying 3D ICs: the pros and cons of going vertical. IEEE Des. Test Comput. 22, 498–510 (2014)CrossRefGoogle Scholar
  5. 5.
    Petrov, V., Moltchanov, D., Koucheryavy, Y.: Interference and SINR in dense terahertz networks. In: IEEE 82nd Vehicular Technology Conference (VTC Fall), pp. 1–5, September 2015Google Scholar
  6. 6.
    Petrov, V., Moltchanov, D., Koucheryavy, Y.: On the efficiency of spatial channel reuse in ultra-dense THz networks. In: 2015 IEEE Global Communications Conference (GLOBECOM), pp. 1–7, December 2015Google Scholar
  7. 7.
    Hammalund, P.: Haswell: the fourth-generation intel core processor. IEEE Micro 2, 6–20 (2014)CrossRefGoogle Scholar
  8. 8.
    Molka, D.: Memory performance and cache coherency effects on an Intel nehalem multiprocessor system. In: Proceedings of IEEE PACT, pp. 78–86 (2009)Google Scholar
  9. 9.
    Intel 64 and IA-32 architectures software developers manual combined volumes. Technical specifications, Intel Corporation (2014)Google Scholar
  10. 10.
    Perf: Technical report. https://perf.wiki.kernel.org. Accessed 02 Sept 2015
  11. 11.
    Intel Performance Counter Monitor: Software tool, Intel Corporation. http://www.intel.com/software/pcm. Accessed 02 Sept 2015
  12. 12.
    MARSSx86 - micro-architectural and system simulator for x86-based systems. Software package, GNU License. http://marss86.org/marss86/. Accessed 02 Sept 2015
  13. 13.
    Binkert, N.: The Gem5 simulator. ACM SIGARCH Comput. Archit. News 39, 1–7 (2011)CrossRefGoogle Scholar
  14. 14.
    Sanches, D., Kozyrakis, C.: ZSim: fast and accurate microarchitectural simulation of thousand-core systems. In: Proceedings of ACM ISCA, pp. 475–486 (2013)Google Scholar
  15. 15.
    The structural simulation kit (SST). In: Proceedings of ACM ISCA, Tutorial. http://www.ece.cmu.edu/calcm/isca2015. Accessed 02 Sept 2015
  16. 16.
    Yotov, K., Pingali, K., Stodghill, P.: Automatic measurement of memory hierarchy parameters. In: Proceedings of ACM SIGMETRICS, p. 181 (2005)Google Scholar
  17. 17.
    Staelin, C.: LMBench: an extensible micro-benchmark suite. Softw. Pract. Exp. 35(11), 1079–1105 (2011)CrossRefGoogle Scholar

Copyright information

© Springer International Publishing AG 2016

Authors and Affiliations

  • Dmitri Moltchanov
    • 1
  • Arkady Kluchev
    • 2
  • Pavel Kustarev
    • 2
  • Karolina Borunova
    • 3
  • Alexey Platunov
    • 2
  1. 1.Department of Communications EngineeringTampere University of TechnologyTampereFinland
  2. 2.Department of Embedded SystemsITMO UniversitySt.-PetersburgRussia
  3. 3.Faculty of Infocommunications Networks and SystemSt.-Petersburg State University of TelecommunicationsSt.-PetersburgRussia

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