Understanding the Memory Consumption of the MiBench Embedded Benchmark

  • Antoine BlinEmail author
  • Cédric Courtaud
  • Julien Sopena
  • Julia Lawall
  • Gilles Muller
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9944)


Complex embedded systems today commonly involve a mix of real-time and best-effort applications. The recent emergence of small low-cost commodity multi-core processors raises the possibility of running both kinds of applications on a single machine, with virtualization ensuring that the best-effort applications cannot steal CPU cycles from the real-time applications. Nevertheless, memory contention can introduce other sources of delay, that can lead to missed deadlines. In this paper, we analyze the sources of memory consumption for the real-time applications found in the MiBench embedded benchmark suite.


  1. 1.
    NXP boards.
  2. 2.
  3. 3.
    OProfile - a system profiler for Linux.
  4. 4.
    perf: Linux profiling with performance counters.
  5. 5.
  6. 6.
  7. 7.
    ARM. ARM Architecture Reference Manual ARMv7-A—R, rev C.b, November 2012Google Scholar
  8. 8.
    ARM. Cortex-A9 Technical Reference Manual, rev r4p1, June 2012Google Scholar
  9. 9.
    ARM. Level 2 Cache Controller L2C–310 TRM, rev r3p3, June 2012Google Scholar
  10. 10.
    ARM. Cortex-A9 MPCore Technical Reference Manual, June rev r4p1 (2012)Google Scholar
  11. 11.
    Ballabriga, C., Cassé, H., Rochange, C., Sainrat, P.: OTAWA: an open toolbox for adaptive WCET analysis. In: Min, S.L., Pettit, R., Puschner, P., Ungerer, T. (eds.) SEUS 2010. LNCS, vol. 6399, pp. 35–46. Springer, Heidelberg (2010)CrossRefGoogle Scholar
  12. 12.
    Barham, P., Dragovic, B., Fraser, K., Hand, S., Harris, T., Ho, A., Neugebauer, R., Pratt, I., Warfield, A.: Xen and the art of virtualization. In: SOSP (2003)Google Scholar
  13. 13.
    Blin, A., Courtaud, C., Sopena, J., Lawall, J., Muller, G.: Maximizing parallelism without exploding deadlines in a mixed criticality embedded system. Technical report RR-8838, INRIA, January 2016Google Scholar
  14. 14.
    Boniol, F., Cassé, H., Noulard, E., Pagetti, C.: Deterministic execution model on COTS hardware. In: Herkersdorf, A., Römer, K., Brinkschulte, U. (eds.) ARCS 2012. LNCS, vol. 7179, pp. 98–110. Springer, Heidelberg (2012)CrossRefGoogle Scholar
  15. 15.
    Fisher, S.: Certifying applications in a multi-core environment: the world’s first multi-core certification to SIL 4. In: SYSGO AG (2014)Google Scholar
  16. 16.
    Fürst, S., Mössinger, J., Bunzel, S., Weber, T., Kirschke-Biller, F., Heitkämper, P., Kinkelin, G., Nishikawa, K., Lange, K.: Autosar-a worldwide standard is on the road. In: 14th International VDI Congress Electronic Systems for Vehicles (2009)Google Scholar
  17. 17.
    Ghosh, S., Martonosi, M., Malik, S.: Cache miss equations: a compiler framework for analyzing and tuning memory behavior. TOPLAS 21(4), 703–746 (1999)CrossRefGoogle Scholar
  18. 18.
    Guthaus, M.R., Ringenberg, J.S., Ernst, D., Austin, T.M., Mudge, T., Brown, R.B.: MiBench: a free, commercially representative embedded benchmark suite. In: EEE International Workshop on Workload Characterization, pp. 3–14 (2001)Google Scholar
  19. 19.
    Jean, X., Gatti, M., Faura, D., Pautet, L., Robert, T.: A software approach for managing shared resources in multicore IMA systems. In: DASC, October 2013Google Scholar
  20. 20.
    Lachaize, R., Lepers, B., Quéma, V., et al.: MemProf: a memory profiler for NUMA multicore systems. In: USENIX Annual Technical Conference, pp. 53–64 (2012)Google Scholar
  21. 21.
    Nowotsch, J., Paulitsch, M.: Leveraging multi-core computing architectures in avionics. In: EDCC, pp. 132–143, MayGoogle Scholar
  22. 22.
    S. NXP. i.MX 6Dual/6Quad Processor Reference Manual, rev 1, April 2013Google Scholar
  23. 23.
    Obermaisser, R., El Salloum, C., Huber, B., Kopetz, H.: From a federated to an integrated automotive architecture. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 28(7), 956 (2009)CrossRefGoogle Scholar
  24. 24.
    Pellizzoni, R., Betti, E., Bak, S., Yao, G., Criswell, J., Caccamo, M., Kegley, R.: A predictable execution model for COTS-based embedded systems. In: RTAS (2011)Google Scholar
  25. 25.
    Peter, S., Baumann, A., Roscoe, T., Barham, P., Isaacs, R.: 30 seconds is not enough!: a study of operating system timer usage. In: EuroSys (2008)Google Scholar
  26. 26.
    Yun, H., Yao, G., Pellizzoni, R., Caccamo, M., Sha, L.: MemGuard: memory bandwidth reservation system for efficient performance isolation in multi-core platforms. In: IEEE 19th RTAS, pp. 55–64. IEEE (2013)Google Scholar

Copyright information

© Springer International Publishing AG 2016

Authors and Affiliations

  • Antoine Blin
    • 1
    • 2
    Email author
  • Cédric Courtaud
    • 1
  • Julien Sopena
    • 1
  • Julia Lawall
    • 1
  • Gilles Muller
    • 1
  1. 1.Sorbonne Universités, Inria, UPMC, LIP6ParisFrance
  2. 2.Renault S.A.SParisFrance

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