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Thin Die Fabrication and Applications to Wafer Level System Integration

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Materials for Advanced Packaging

Abstract

Thin die fabrication is an essential part of wafer processes in 3D IC, interposer, and fan-in and fan-out wafer level packaging technologies. A review on the available process technologies including temporary bonding, de-bonding, wafer thinning, thin wafer handling, thin wafer backside processes, and die singulation are discussed and summarized in this chapter. The fabricated thin dies are integrated and assembled using wafer level system integration (WLSI) processes. A brief summary on two important WLSI technology platforms, namely Chip-on-Wafer-on-Substrate (CoWoS™) and Integrated Fan-Out (InFO) are presented as a conclusion for thin die fabrication and wafer level system integration chapter.

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Author information

Authors and Affiliations

  1. Taiwan Semiconductor Manufacturing Company (TSMC), 168, Park Ave. 2, Hsinchu Science Park, Hsinchu, Taiwan, 30075, R.O.C.

    Doug C. H. Yu Ph.D., Wen-Chih Chiou Ph.D. & Chih Hang Tung

Authors
  1. Doug C. H. Yu Ph.D.
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  2. Wen-Chih Chiou Ph.D.
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  3. Chih Hang Tung
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Corresponding author

Correspondence to Doug C. H. Yu Ph.D. .

Editor information

Editors and Affiliations

  1. Henkel China Co., Ltd, Shanghai, Shanghai, China

    Daniel Lu

  2. Materials Science and Engineering, Georgia Institute of Technology, Atlanta, Georgia, USA

    C.P. Wong

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Yu, D.C.H., Chiou, WC., Tung, C.H. (2017). Thin Die Fabrication and Applications to Wafer Level System Integration. In: Lu, D., Wong, C. (eds) Materials for Advanced Packaging. Springer, Cham. https://doi.org/10.1007/978-3-319-45098-8_6

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  • DOI: https://doi.org/10.1007/978-3-319-45098-8_6

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-45097-1

  • Online ISBN: 978-3-319-45098-8

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