A Maude Framework for Cache Coherent Multicore Architectures

  • Shiji Bijo
  • Einar Broch Johnsen
  • Ka I Pun
  • Silvia Lizeth Tapia Tarifa
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9942)


On shared memory multicore architectures, cache memory is used to accelerate program execution by providing quick access to recently used data, but enables multiple copies of data to co-exist during execution. Although cache coherence protocols ensure that cores do not access stale data, the organisation of data in memory and the scheduling of tasks may significantly influence the performance of a parallel program in this setting. As a step towards understanding how the data organisation impacts the performance of a given parallel program using shared memory, this paper proposes a framework defined in Maude for the executable modelling of program execution on cache coherent multicore architectures, formalising the interactions between cores executing tasks, their caches, and main memory. The framework allows the specification and comparison of program execution with different design choices for the underlying hardware architecture, such as the number of cores, the data layout in main memory, and the cache associativity.


Shared Memory Main Memory Hardware Architecture Reachable State Cache Line 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


We are grateful to the anonymous reviewers for their very thorough reviews and for giving helpful and critical feedback.


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Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  • Shiji Bijo
    • 1
  • Einar Broch Johnsen
    • 1
  • Ka I Pun
    • 1
  • Silvia Lizeth Tapia Tarifa
    • 1
  1. 1.Department of InformaticsUniversity of OsloOsloNorway

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