Implementation of Delay-Based PUFs on Altera FPGAs

  • Linus FeitenEmail author
  • Matthias Sauer
  • Bernd Becker


This chapter focuses on the implementation of delay-based PUFs on Altera FPGAs. While there has been a manifold of publications on how to evaluate and refine PUFs, a thorough description of the required “handicrafts” enabling a novice to enter this exciting research field has so far been missing. The methods shared in this chapter are not just easily extractable from available standard documentation, but have been compiled by the authors over a long period of trials and consultations with the Altera user community. Designing a delay-based PUF on FPGAs requires fine-tuning which is often like diverting the automated design tools from their intended use. For example, the device-specific delays for the PUF response generation are generally gathered from circuitry looking redundant to the bitstream compiler. Therefore, the automatic reduction of such seemingly redundant circuitry must be prevented. The way the circuitry is placed and routed also has a major impact on delay characteristics, so it is necessary to customise this instead of letting the compiler do it automatically. The reader will be walked through all necessary steps by means of a running example enabling them to embark on further experiments on their own. Along the way, the architecture of Altera Cyclone FPGAs is explained and results from the authors’ own experimental studies are shared.


FPGAField Programmable Gate Array Ring Oscillator Delay Element Chip Planner FPGAField Programmable Gate Array Design 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer International Publishing Switzerland 2017

Authors and Affiliations

  1. 1.University of Freiburg, Chair for Computer ArchitectureFreiburgGermany

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