NEO 2015 pp 89-104 | Cite as

Automatic Random Tree Generator on FPGA

  • Carlos Goribar
  • Yazmin Maldonado
  • Leonardo Trujillo
Part of the Studies in Computational Intelligence book series (SCI, volume 663)


In this work we propose the implementation of an automatic random tree generator on an FPGA for genetic programming (GP). While most authors in specialized literature avoid the use of the tree data structure in their implementations of GP on Field Programmable Gate Arrays (FPGAs), due to the impossibility of using pointers (references) in the Very High Speed Integrated Circuit Hardware Description Language (VHDL), we propose two methods for a single matrix implementation and one for a vector implementation. All trees in the population are created in concurrent processes leading to significant time savings. We present pseudocode and results of hardware consumption for matrix and vector implementations. Results show that up to 100 trees can be implemented in a Spartan-6 FPGA using the representation of one tree in a single matrix in parallel processes. Moreover, this implementation requires less resources than the apparently simpler vector representation.


FPGA VHDL Parallelization 



The authors want to thank the Instituto Tecnológico de Tijuana, and PRODEP with the projet “Reducción del área de sistemas reconfigurables” with number ITTIJ-PTC-007 for supporting our research activities. Also wants to thank the CONACYT for the funding for this work with the project No. 178323, the TecNM(México) Research projects 5861.16P, Prodep(México) ITTIJ-PTC-007, and the FP7-Marie Curie-IRSES 2013 European Commission program through project ACoBSEC with contract No. 612689.


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Copyright information

© Springer International Publishing Switzerland 2017

Authors and Affiliations

  • Carlos Goribar
    • 1
  • Yazmin Maldonado
    • 1
  • Leonardo Trujillo
    • 1
  1. 1.Posgrado en Ciencias de la IngenieríaInstituto Tecnológico de TijuanaTijuanaMexico

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