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End-to-End Verification of Open image in new window Processors with ISA-Formal

  • Alastair Reid
  • Rick Chen
  • Anastasios Deligiannis
  • David Gilday
  • David Hoyes
  • Will Keen
  • Ashan Pathirane
  • Owen Shepherd
  • Peter Vrabel
  • Ali Zaidi
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9780)

Abstract

Despite 20+ years of research on processor verification, it remains hard to use formal verification techniques in commercial processor development. There are two significant factors: scaling issues and return on investment. The scaling issues include the size of modern processor specifications, the size/complexity of processor designs, the size of design/verification teams and the (non)availability of enough formal verification experts. The return on investment issues include the need to start catching bugs early in development, the need to continue catching bugs throughout development, and the need to be able to reuse verification IP, tools and techniques across a wide range of design styles.

This paper describes how ARM has overcome these issues in our Instruction Set Architecture Formal Verification framework “ISA-Formal.” This is an end-to-end framework to detect bugs in the datapath, pipeline control and forwarding/stall logic of processors. A key part of making the approach scale is use of a mechanical translation of ARM’s Architecture Reference Manuals to Verilog allowing the use of commercial model-checkers. ISA-Formal has proven especially effective at finding micro-architecture specific bugs involving complex sequences of instructions.

An essential feature of our work is that it is able to scale all the way from simple 3-stage microcontrollers, through superscalar in-order processors up to out-of-order processors. We have applied this method to 8 different ARM processors spanning all stages of development up to release. In all processors, this has found bugs that would have been hard for conventional simulation-based verification to find and ISA-Formal is now a key part of ARM’s formal verification strategy.

To the best of our knowledge, this is the most broadly applicable formal verification technique for verifying processor pipeline control in mainstream commercial use.

Keywords

Register File Formal Verification Forwarding Path Verification Technique Bound Model Check 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Aagaard, M.D., Cook, B., Day, N.A., Jones, R.B.: A framework for microprocessor correctness statements. In: Margaria, T., Melham, T.F. (eds.) CHARME 2001. LNCS, vol. 2144, pp. 433–448. Springer, Heidelberg (2001). http://dl.acm.org/citation.cfm?id=646705.702043 CrossRefGoogle Scholar
  2. 2.
    Aagaard, M.D., Jones, R.B., Melham, T.F., O’Leary, J.W., Seger, C.-J.H.: A methodology for large-scale hardware verification. In: Johnson, S.D., Hunt Jr., W.A. (eds.) FMCAD 2000. LNCS, vol. 1954, pp. 300–319. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  3. 3.
    ARM Ltd: ARM Architecture Reference Manual (ARMv8, for ARMv8-A architecture profile). ARM Ltd (2013)Google Scholar
  4. 4.
    ARM Ltd: (In Preparation) ARM Architecture Reference Manual (ARMv8, for ARMv8-M architecture profile). ARM Ltd (2016)Google Scholar
  5. 5.
    Burch, J.R., Dill, D.L.: Automatic verification of pipelined microprocessor control. In: Dill, D.L. (ed.) CAV 1994. LNCS, vol. 818, pp. 68–80. Springer, Heidelberg (1994). http://dl.acm.org/citation.cfm?id=647763.735662 CrossRefGoogle Scholar
  6. 6.
    Fox, A., Myreen, M.O.: A trustworthy monadic formalization of the ARMv7 instruction set architecture. In: Kaufmann, M., Paulson, L.C. (eds.) ITP 2010. LNCS, vol. 6172, pp. 243–258. Springer, Heidelberg (2010). doi: 10.1007/978-3-642-14052-5_18 CrossRefGoogle Scholar
  7. 7.
    Higgins, J.T., Aagaard, M.D.: Simplifying design and verification for structural hazards and datapaths in pipelined circuits. In: Ninth IEEE International Proceedings of the High-Level Design Validation and Test Workshop, HLDVT 2004, pp. 31–36 (2004). http://dx.doi.org/10.1109/HLDVT.2004.1431229
  8. 8.
    Hunt Jr., W.A., Sawada, J.: Verifying the FM9801 microarchitecture. IEEE Micro 19(3), 47–55 (1999). doi: 10.1109/40.768503 CrossRefGoogle Scholar
  9. 9.
    Jhalal, R., McMillan, K.L.: Microarchitecture verification by compositional model checking. In: Berry, G., Comon, H., Finkel, A. (eds.) CAV 2001. LNCS, vol. 2102, p. 396. Springer, Heidelberg (2001). doi: 10.1007/3-540-44585-4_40 CrossRefGoogle Scholar
  10. 10.
    Kaivola, R., et al.: Replacing testing with formal verification in Intel\(^{\textregistered }\) Core\(^\text{ TM }\) i7 processor execution engine validation. In: Bouajjani, A., Maler, O. (eds.) CAV 2009. LNCS, vol. 5643, pp. 414–429. Springer, Heidelberg (2009). http://dx.doi.org/10.1007/978-3-642-02658-4_32 CrossRefGoogle Scholar
  11. 11.
    KiranKumar, V., Gupta, A., Ghughal, R.: Symbolic trajectory evaluation: the primary validation vehicle for next generation Intel processor graphics FPU. In: Formal Methods in Computer-Aided Design (FMCAD), pp. 149–156. IEEE (2012)Google Scholar
  12. 12.
    Kroening, D., Paul, W., Mueller, S.: Proving the correctness of pipelined micro-architectures. In: Waldschmidt, K., Grimm, C. (eds.) Proceedings of ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, pp. 89–98. VDE Verlag (2000)Google Scholar
  13. 13.
    Lahiri, S.K., Bryant, R.E.: Deductive verification of advanced out-of-order microprocessors. In: Hunt Jr., W.A., Somenzi, F. (eds.) CAV 2003. LNCS, vol. 2725, pp. 341–354. Springer, Heidelberg (2003). doi: 10.1007/978-3-540-45069-6_33 CrossRefGoogle Scholar
  14. 14.
    Lahiri, S.K., Pixley, C., Albin, K.: Experience with term level modeling and verification of the M*CORE\({}^{TM}\) microprocessor core. In: Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, Monterey, California, USA, 7–9 November 2001, pp. 109–114 (2001). http://dx.doi.org/10.1109/HLDVT.2001.972816
  15. 15.
    Malik, N., Eickemeyer, R.J., Vassiliadis, S.: Interlock collapsing ALU for increased instruction-level parallelism. In: Proceedings of the 25th Annual International Symposium on Microarchitecture, pp. 149–157. MICRO 25, CA (1992). http://dl.acm.org/citation.cfm?id=144953.145794
  16. 16.
    McMillan, K.L.: Verification of an implementation of Tomasulo’s algorithm by compositional model checking. In: Vardi, M.Y. (ed.) CAV 1998. LNCS, vol. 1427, pp. 110–121. Springer, Heidelberg (1998). http://dl.acm.org/citation.cfm?id=647767.733764 CrossRefGoogle Scholar
  17. 17.
    Reid, A.: Creating trustworthy specifications of ARM v8-A and v8-M system level architecture. In: preparation (2016)Google Scholar
  18. 18.
    Slobodová, A., Davis, J., Swords, S., Hunt Jr., W.: A flexible formal verification framework for industrial scale validation. In: 2011 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE), pp. 89–97. IEEE (2011)Google Scholar
  19. 19.
    Srinivasan, S.K.: Automatic refinement checking of pipelines with out-of-order execution. IEEE Trans. Comput. 59(8), 1138–1144 (2010)MathSciNetCrossRefGoogle Scholar
  20. 20.
    Stewart, D., Gilday, D., Nevill, D., Roberts, T.: Processor memory system verification using DOGReL: a language for specifying end-to-end properties. In: International Workshop on Design and Implementation of Formal Tools and Systems, DIFTS 2014 (2014)Google Scholar
  21. 21.
    Windley, P.J.: Formal modeling and verification of microprocessors. IEEE Trans. Comput. 44(1), 54–72 (1995)CrossRefzbMATHGoogle Scholar

Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  • Alastair Reid
    • 1
  • Rick Chen
    • 1
  • Anastasios Deligiannis
    • 1
  • David Gilday
    • 1
  • David Hoyes
    • 1
  • Will Keen
    • 1
  • Ashan Pathirane
    • 1
  • Owen Shepherd
    • 1
  • Peter Vrabel
    • 1
  • Ali Zaidi
    • 1
  1. 1.ARM LimitedCambridgeUK

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