Bounded Cycle Synthesis

Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9779)


We introduce a new approach for the synthesis of Mealy machines from specifications in linear-time temporal logic (LTL), where the number of cycles in the state graph of the implementation is limited by a given bound. Bounding the number of cycles leads to implementations that are structurally simpler and easier to understand. We solve the synthesis problem via an extension of SAT-based bounded synthesis, where we additionally construct a witness structure that limits the number of cycles. We also establish a triple-exponential upper and lower bound for the potential blow-up between the length of the LTL formula and the number of cycles in the state graph.


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Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  1. 1.Reactive Systems GroupSaarland UniversitySaarbrückenGermany

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