TCU: A Multi-Objective Hardware Thread Mapping Unit for HPC Clusters

  • Ravi Kumar Pujari
  • Thomas Wild
  • Andreas Herkersdorf
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9697)

Abstract

Meeting multiple, partially orthogonal optimization targets during thread scheduling on HPC and manycore platforms simultaneously, like maximizing CPU performance, meeting deadlines of time critical tasks, minimizing power and securing thermal resilience, is a major challenge because of associated scalability and thread management overhead. We tackle these challenges by introducing the Thread Control Unit (TCU), a configurable, low-latency, low-overhead hardware thread mapper in compute nodes of an HPC cluster. The TCU takes various sensor information into account and can map threads to 4–16 CPUs of a compute node within a small and bounded number of clock cycles in round-robin, single- or multi-objective manner. The TCU design can consider not just load balancing or performance criteria but also physical constraints like temperature limits, power budgets and reliability aspects. Evaluations of different mapping policies show that multi-objective thread mapping provides about 10 to 40 % less mapping latency for periodic workloads compared to single-objective or round-robin policies. For bursty workloads under high load conditions, a 20 % reduction is achieved.

The TCU macro has a mere 9 % hardware area overhead and achieves more than 150 k thread mappings per second on an FPGA prototype of a RISC quad-core compute node operating at moderate 50 MHz. A 45 nm technology ASIC realization of TCU can operate well above 1 GHz and support up to 3.15 million thread mappings per second.

Keywords

Hardware scheduler Thread mapper Multi-objective MPSoC HPC Manycore systems 

Notes

Acknowledgement

This work was supported by the German Research Foundation (DFG) as part of the Transregional Collaborative Research Center “Invasive Computing” (SFB/TR 89).

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Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  • Ravi Kumar Pujari
    • 1
  • Thomas Wild
    • 1
  • Andreas Herkersdorf
    • 1
  1. 1.Institute for Integrated SystemsTechnische Universität MünchenMunichGermany

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