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A Fast Symbolic Transformation Based Algorithm for Reversible Logic Synthesis

  • Mathias Soeken
  • Gerhard W. Dueck
  • D. Michael Miller
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9720)

Abstract

We present a more concise formulation of the transformation based synthesis approach for reversible logic synthesis, which is one of the most prominent explicit ancilla-free synthesis approaches. Based on this formulation we devise a symbolic variant of the approach that allows one to find a circuit in shorter time using less memory for the function representation. We present both a BDD based and a SAT based implementation of the symbolic variant. Experimental results show that both approaches are significantly faster than the state-of-the-art method. We were able to find ancilla-free circuit realizations for large optimally embedded reversible functions for the first time.

Keywords

Reversible circuit synthesis Symbolic methods Binary decision diagrams Boolean satisfiability 

Notes

Acknowledgments

This research was supported by H2020-ERC-2014-ADG 669354 CyberCare and by the European COST Action IC 1405 ‘Reversible Computation’.

References

  1. 1.
    Alhagi, N., Hawash, M., Perkowski, M.A.: Synthesis of reversible circuits with no ancilla bits for large reversible functions specified with bit equations. In: ISMVL, pp. 39–45 (2010)Google Scholar
  2. 2.
    Biere, A., Heule, M., van Maaren, H., Walsh, T. (eds.): Handbook of Satisfiability, Frontiers in Artificial Intelligence and Applications, vol. 185. IOS Press, Amsterdam (2009)Google Scholar
  3. 3.
    Bryant, R.E.: Graph-based algorithms for Boolean function manipulation. IEEE-TC 35(8), 677–691 (1986)zbMATHGoogle Scholar
  4. 4.
    De Vos, A., Rentergem, Y.: Young subgroups for reversible computers. Adv. Math. Commun. 2(2), 183–200 (2008)MathSciNetCrossRefzbMATHGoogle Scholar
  5. 5.
    Eén, N., Mishchenko, A., Amla, N.: A single-instance incremental SAT formulation of proof- and counterexample-based abstraction. In: FMCAD, pp. 181–188 (2010)Google Scholar
  6. 6.
    Große, D., Wille, R., Dueck, G.W., Drechsler, R.: Exact multiple-control Toffoli network synthesis with SAT techniques. TCAD 28(5), 703–715 (2009)Google Scholar
  7. 7.
    Gupta, P., Agrawal, A., Jha, N.K.: An algorithm for synthesis of reversible logic circuits. TCAD 25(11), 2317–2330 (2006)Google Scholar
  8. 8.
    Järvisalo, M., Biere, A., Heule, M.: Blocked clause elimination. In: Esparza, J., Majumdar, R. (eds.) TACAS 2010. LNCS, vol. 6015, pp. 129–144. Springer, Heidelberg (2010)CrossRefGoogle Scholar
  9. 9.
    Miller, D.M., Maslov, D., Dueck, G.W.: A transformation based algorithm for reversible logic synthesis. In: DAC, pp. 318–323 (2003)Google Scholar
  10. 10.
    Plaisted, D.A., Greenbaum, S.: A structure-preserving clause form translation. JSC 2(3), 293–394 (1986)MathSciNetzbMATHGoogle Scholar
  11. 11.
    Sinz, C.: Towards an optimal CNF encoding of boolean cardinality constraints. In: CP, pp. 827–831 (2005)Google Scholar
  12. 12.
    Soeken, M., Chattopadhyay, A.: Fredkin-enabled transformation-based reversible logic synthesis. In: ISMVL, pp. 60–65 (2015)Google Scholar
  13. 13.
    Soeken, M., Frehse, S., Wille, R., Drechsler, R.: RevKit: a toolkit for reversible circuit design. Multiple-Valued Logic Soft Comput. 18(1), 55–65 (2012)Google Scholar
  14. 14.
    Soeken, M., Tague, L., Dueck, G.W., Drechsler, R.: Ancilla-free synthesis of large reversible functions using binary decision diagrams. JSC 73, 1–26 (2016)MathSciNetzbMATHGoogle Scholar
  15. 15.
    Soeken, M., Wille, R., Hilken, C., Przigoda, N., Drechsler, R.: Synthesis of reversible circuits with minimal lines for large functions. In: ASP-DAC, pp. 85–92 (2012)Google Scholar
  16. 16.
    Soeken, M., Wille, R., Keszocze, O., Miller, D.M., Drechsler, R.: Embedding of large Boolean functions for reversible logic. JETC (2015). arXiv:1408.3586
  17. 17.
    Takahashi, Y., Tani, S., Kunihiro, N.: Quantum addition circuits and unbounded fan-out. Quantum Inf. Comput. 10(9&10), 872–890 (2010)MathSciNetzbMATHGoogle Scholar
  18. 18.
    Touati, H.J., Savoj, H., Lin, B., Brayton, R.K., Sangiovanni-Vincentelli, A.L.: Implicit state enumeration of finite state machines using BDDs. In: ICCAD, pp. 130–133 (1990)Google Scholar
  19. 19.
    Wegener, I.: The size of reduced OBDDs and optimal read-once branching programs for almost all Boolean functions. IEEE Trans. Comput. 43(11), 1262–1269 (1994)MathSciNetCrossRefzbMATHGoogle Scholar
  20. 20.
    Wille, R., Große, D., Dueck, G.W., Drechsler, R.: Reversible logic synthesis with output permutation. In: VLSI Design, pp. 189–194 (2009)Google Scholar

Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  • Mathias Soeken
    • 1
  • Gerhard W. Dueck
    • 2
  • D. Michael Miller
    • 3
  1. 1.Integrated Systems Laboratory, EPFLLausanneSwitzerland
  2. 2.University of New BrunswickFrederictonCanada
  3. 3.University of VictoriaVictoriaCanada

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