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The Macro-DSE for HPC Processing Unit: The Physical Constraints Perspective

  • Yuxing TangEmail author
  • Lei Wang
  • Yu Deng
  • Xiaoqiang Ni
  • Qiang Dou
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9663)

Abstract

Because of the popularity of big data and cloud computing, the evolution of microarchitecture has to concentrated on raw computing ability, throughput, low power and cost at the same time. Due to the huge Non-recurring engineering costs, computer architects and processor designers rely on the simulation tools and models to optimize the main processing unit. Design space exploration (DSE) methodology is responsible to filter all the possible choices. However, thousands of parameters for current multi-core processor make it too expensive to complete the exhausting search. The future high performance computing (HPC) no longer insist on peak double precision performance (DFP) only, but also on high throughput and light-weight. Depending on the various details from the number of cores to the individual pipeline buffer size, we can divide the DSE problem into macro and micro level.

In this paper, we focus on the macro-DSE problem around choosing the right style for the processing core design. Firstly, we extended McPAT, the de facto DSE tools to support from 65 nm to 16 nm technology and up to 256 Cores. Based on the physical design constraints: chip area, power and balance design request, we examine and explore the design of future processing unit of high performance. Although traditional HPC pursued the peak performance only, our DSE results show the physical constrain will direct the processing unit of future HPC to limited choice. The experiment results show that with only 74.8 % increasing in chip die area and 3.8 % increasing in power, one many-core design can archive 4 times peak performance both in INT and FP, and 285.6 % increasing in performance/power efficiency than another. The key insight of our experiment indicates that unique type of processing core can be the best choice depending on the specific physical design plan.

Keywords

Processor Design space HPC Cloud 

Notes

Acknowledgements

We thanks the other cpu@nudt team numbers that provide architecture, microarchitecture and physical design parameters of various processor. This work is supported in part by NSFC grants No. 61272139 and National Science and Technology Major Project HGJ-2015ZX01028001-001.

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Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  • Yuxing Tang
    • 1
    Email author
  • Lei Wang
    • 1
  • Yu Deng
    • 1
  • Xiaoqiang Ni
    • 1
  • Qiang Dou
    • 1
  1. 1.School of ComputerNational University of Defense TechnologyChangshaChina

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