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A VHDL-Based Modeling of Network Interface Card Buffers: Design and Teaching Methodology

  • Godofredo R. Garay
  • Andrei Tchernykh
  • Alexander Yu. Drozdov
  • Sergey V. Novikov
  • Victor E. Vladislavlev
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 595)

Abstract

The design of High Performance Computing (HPC) relies to a large extent on simulations to optimize components of such complex systems. A key hardware component of the interconnection network in HPC environments is the Network Interface Card (NIC). In spite of the popularity of simulation-based approaches in the computer architecture domain, few authors have focused on simulators design methodologies. In this paper, we describe the stages of implementing a simulation model to solve a real problem—modeling NIC buffer. We present a general methodology for helping users to build Hardware Description Language (HDL)/SystemC models targeted to fulfil features such as performance evaluation of compute nodes. The developed VHDL model allows reproducibility and can be used as a tool in the area of HPC education.

Keywords

Simulation Design methodology VHDL NIC Real-Time Calculus 

Notes

Acknowledgments

This work is supported by the Ministry of Education and Science of Russian Federation under contract No02.G25.31.0061 12/02/2013 (Government Regulation No 218 from 09/04/2010).

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Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  • Godofredo R. Garay
    • 1
  • Andrei Tchernykh
    • 2
  • Alexander Yu. Drozdov
    • 3
  • Sergey V. Novikov
    • 3
  • Victor E. Vladislavlev
    • 3
  1. 1.Camagüey UniversityCamagüeyCuba
  2. 2.CICESE Research CenterEnsenadaMexico
  3. 3.Moscow Institute of Physics and TechnologyMoscowRussia

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