Advertisement

Parallel Programs Scheduling with Architecturally Supported Regions

  • Łukasz Maśko
  • Marek Tudruj
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9574)

Abstract

Scheduling of programs for hierarchical architectures of Chip Multi-Processor (CMP) modules interconnected by global data networks is the subject of this paper. The CMP modules are of double nature: architecturally specialized modules which execute time-critical computations and standard CMP modules which interconnect the specialized ones. Inside application programs, so called architecturally supported regions are identified meant for efficient execution on dedicated architecturally supported modules. Programs are represented by macro dataflow graphs built of architecturally supported nodes and program glue nodes. The paper proposes a new task scheduling algorithm for programs meant for execution in such CMP-based systems. The algorithm is based on list scheduling with modified ETF (Earliest Task First) heuristics. It is assessed by experiments based on simulation of program execution which shows parallel speedup improvements.

Keywords

Parallel programming Program graph scheduling Parallel architectures Heterogeneity 

References

  1. 1.
    Owens, J.D., et al.: Research challenges for on-chip interconnection networks. IEEE MICRO 27, 96–108 (2007)CrossRefGoogle Scholar
  2. 2.
    Kundu, S., Peh, L.S.: On-chip interconnects for multicores. IEEE MICRO 25, 3–5 (2007)CrossRefGoogle Scholar
  3. 3.
    Hwang, J.-J., Chow, Y.-C., Anger, F.D., Lee, C.-Y.: Scheduling precedence graphs in systems with interprocessor communication times. SIAM J. Comput. 18(2), 244–257 (1989)MathSciNetCrossRefzbMATHGoogle Scholar
  4. 4.
    Yu-Kwong, K., Ishfaq, A.: Benchmarking and comparison of the task graph scheduling algorithms. J. Parallel Distrib. Comput. 59, 381–422 (1999)CrossRefzbMATHGoogle Scholar
  5. 5.
    Sinnen, O.: Task Scheduling for Parallel Systems. Wiley, England (2007)CrossRefGoogle Scholar
  6. 6.
    Błażewicz, J., Ecker, K.H., Pesch, E., Schmidt, G., Weglarz, J.: Handbook on Scheduling. International Handbooks on Information Systems. Springer, Heidelberg (2007)zbMATHGoogle Scholar
  7. 7.
    Topcuoglu, H., Hariri, S., Min-You, W.: Performance-effective, low-complexity task scheduling for heterogeneous computing. IEEE Trans. Parallel, Distrib. Syst. 13(3), 260–274Google Scholar
  8. 8.
    Masko, Ł., Dutot, P.F., Mounié, G., Trystram, D., Tudruj, M.: Scheduling moldable tasks for dynamic SMP clusters in SoC technology. In: Wyrzykowski, R., Dongarra, J., Meyer, N., Waśniewski, J. (eds.) PPAM 2005. LNCS, vol. 3911, pp. 879–887. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  9. 9.
    Maśko, Ł., Tudruj, M.: Task scheduling for SoC-Based dynamic SMP clusters with communication on the fly. In: 7th International Symposium on Parallel and Distributed Computing, ISPDC, pp. 99–10. IEEE CS (2008)Google Scholar
  10. 10.
    Tudruj, M., Maśko, Ł.: Scheduling parallel programs based on architecture–supported regions. In: Wyrzykowski, R., Dongarra, J., Karczewski, K., Waśniewski, J. (eds.) PPAM 2011, Part II. LNCS, vol. 7204, pp. 51–60. Springer, Heidelberg (2012)CrossRefGoogle Scholar

Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  1. 1.Institute of Computer SciencePolish Academy of SciencesWarsawPoland
  2. 2.Polish-Japanese Academy of Information TechnologyWarsawPoland

Personalised recommendations