Thermal Safe Power: Efficient Thermal-Aware Power Budgeting for Manycore Systems in Dark Silicon

  • Santiago PaganiEmail author
  • Heba Khdr
  • Jian-Jia Chen
  • Muhammad Shafique
  • Minming Li
  • Jörg Henkel


Chip manufacturers commonly provide the Thermal Design Power (TDP) for a specific chip. The cooling solution is generally designed to dissipate this power level. But because TDP is not necessarily the maximum power that can be applied, in order to avoid the chip from possible overheating, chips are operated with Dynamic Thermal Management (DTM) techniques. To avoid excessive triggers of DTM, usually, system designers also use TDP as power constraint. However, using a single and constant value as power constraint, e.g., TDP, can result in significant performance losses in homogeneous and heterogeneous manycore systems. Having better power budgeting techniques is a major step towards dealing with the dark silicon problem. In this chapter, we present a power budget concept called Thermal Safe Power (TSP), which is an abstraction that provides safe power and power density constraints as a function of the number of simultaneously active cores. Executing cores at any power consumption below TSP ensures that DTM is not triggered. TSP can be computed offline for the worst cases, or online for a particular mapping of cores. TSP can also serve as a fundamental tool for guiding task partitioning and core mapping decisions, specially when core heterogeneity or timing guarantees are involved. Moreover, TSP results in dark silicon estimations which are less pessimistic than estimations using constant power budgets.


Power Consumption Power Constraint Active Core Core Mapping Power Budget 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



This work was partly supported by the German Research Foundation (DFG) as part of the Transregional Collaborative Research Centre Invasive Computing [SFB/TR 89], by Baden Württemberg MWK Juniorprofessoren-Programms, and by a grant from the Research Grants Council of the Hong Kong Special Administrative Region, China [Project CityU 117913].


  1. 1.
    C. Bienia, S. Kumar, J.P. Singh, K. Li, The PARSEC benchmark suite: characterization and architectural implications, in PACT (2008), pp. 72–81Google Scholar
  2. 2.
    N. Binkert, B. Beckmann, G. Black, S.K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D.R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M.D. Hill, D.A. Wood, The gem5 simulator. ACM SIGARCH Comput. Archit. News 39 (2), 1–7 (2011)CrossRefGoogle Scholar
  3. 3.
    H. Bokhari, H. Javaid, M. Shafique, J. Henkel, S. Parameswaran, darkNoC: designing energy-efficient network-on-chip with multi-Vt cells for dark silicon, in DAC (2014), pp. 161:1–161:6Google Scholar
  4. 4.
    J. Casazza, First the tick, now the tock: Intel microarchitecture (Nehalem). White paper, Intel Corporation, 2009Google Scholar
  5. 5.
    J. Cebrian, L. Natvig, J. Meyer, Improving energy efficiency through parallelization and vectorization on intel core i5 and i7 processors, in SC Companion (2012), pp. 675–684Google Scholar
  6. 6.
    J. Charles, P. Jassi, N.S. Ananth, A. Sadat, A. Fedorova, Evaluation of the intel core i7 turbo boost feature, in IISWC (2009), pp. 188–197Google Scholar
  7. 7.
    T. Ebi, D. Kramer, W. Karl, J. Henkel, Economic learning for thermal-aware power budgeting in many-core architectures, in CODES+ISSS (2011), pp. 189–196Google Scholar
  8. 8.
    H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam, D. Burger, Dark silicon and the end of multicore scaling, in ISCA (2011), pp. 365–376Google Scholar
  9. 9.
    A. Grenat, S. Pant, R. Rachala, S. Naffziger, 5.6 adaptive clocking system for improved power efficiency in a 28 nm x86-64 microprocessor, in ISSCC (2014), pp. 106–107Google Scholar
  10. 10.
    W. Huang, S. Ghosh, S. Velusamy, K. Sankaranarayanan, K. Skadron, M.R. Stan, HotSpot: a compact thermal modeling methodology for early-stage VLSI design. IEEE Trans. VLSI Syst. 14 (5), 501–513 (2006)CrossRefGoogle Scholar
  11. 11.
    Intel Corporation, Dual-core intel xeon processor 5100 series datasheet, revision 003, August 2007.Google Scholar
  12. 12.
    Intel Corporation, Intel turbo boost technology in intel CoreTM microarchitecture (nehalem) based processors. White paper, November 2008Google Scholar
  13. 13.
  14. 14.
    F. Kriebel, S. Rehman, D. Sun, M. Shafique, J. Henkel, ASER: adaptive soft error resilience for reliability-heterogeneous processors in the dark silicon era, in DAC (2014), pp. 12:1–12:6Google Scholar
  15. 15.
    E. Kultursay, K. Swaminathan, V. Saripalli, V. Narayanan, M.T. Kandemir, S. Datta, Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores, in CODES+ISSS (2012), pp. 245–254Google Scholar
  16. 16.
    J. Lee, N.S. Kim, Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating, in DAC (2009), pp. 47–50Google Scholar
  17. 17.
    S. Li, J.-H. Ahn, R. Strong, J. Brockman, D. Tullsen, N. Jouppi, McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures, in MICRO (2009), pp. 469–480Google Scholar
  18. 18.
    T. Muthukaruppan, M. Pricopi, V. Venkataramani, T. Mitra, S. Vishin, Hierarchical power management for asymmetric multi-core in dark silicon era, in DAC (2013), pp. 174:1–174:9Google Scholar
  19. 19.
    S. Nussbaum, AMD trinity APU, in Hot Chips (2012)Google Scholar
  20. 20.
    S. Pagani, H. Khdr, W. Munawar, J.-J. Chen, M. Shafique, M. Li, J. Henkel, TSP: thermal safe power - efficient power budgeting for many-core systems in dark silicon, in The International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2014, pp. 10:1–10:10Google Scholar
  21. 21.
    S. Pagani, J.-J. Chen, M. Shafique, J. Henkel, MatEx: efficient transient and peak temperature computation for compact thermal models, in The 18th Design, Automation and Test in Europe (DATE), March 2015, pp. 1515–1520Google Scholar
  22. 22.
    S. Pagani, J.-J. Chen, M. Shafique, J. Henkel, Thermal-aware power budgeting for dark silicon chips, in the 2nd Workshop on Low-Power Dependable Computing (LPDC), Part of the 6th International Green and Sustainable Computing Conference (IGSC), December 2015Google Scholar
  23. 23.
    B. Raghunathan, S. Garg, Job arrival rate aware scheduling for asymmetric multi-core servers in the dark silicon era, in CODES+ISSS (2014)Google Scholar
  24. 24.
    B. Raghunathan, Y. Turakhia, S. Garg, D. Marculescu, Cherry-picking: Exploiting process variations in dark-silicon homogeneous chip multi-processors, in DATE (2013), pp. 39–44Google Scholar
  25. 25.
    E. Rotem, A. Naveh, D. Rajwan, A. Ananthakrishnan, E. Weissmann, Power-management architecture of the intel microarchitecture code-named sandy bridge. Micro, IEEE 32 (2), 20–27 (2012)CrossRefGoogle Scholar
  26. 26.
    M. Shafique, S. Garg, J. Henkel, D. Marculescu, The EDA challenges in the dark silicon era: temperature, reliability, and variability perspectives, in DAC (2014), pp. 185:1–185:6Google Scholar
  27. 27.
    C. Tan, T. Muthukaruppan, T. Mitra, L. Ju, Approximation-aware scheduling on heterogeneous multi-core architectures, in ASP-DAC, January 2015, pp. 618–623Google Scholar

Copyright information

© Springer International Publishing Switzerland 2017

Authors and Affiliations

  • Santiago Pagani
    • 1
    Email author
  • Heba Khdr
    • 1
  • Jian-Jia Chen
    • 2
  • Muhammad Shafique
    • 1
  • Minming Li
    • 3
  • Jörg Henkel
    • 1
  1. 1.Chair for Embedded Systems (CES)Karlsruhe Institute of Technology (KIT)KarlsruheGermany
  2. 2.Department of InformaticsTU DortmundDortmundGermany
  3. 3.Department of Computer ScienceCity University of Hong Kong (CityU)Hong KongChina

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