A Perspective on Dark Silicon

  • Anil KanduriEmail author
  • Amir M. Rahmani
  • Pasi Liljeberg
  • Ahmed Hemani
  • Axel Jantsch
  • Hannu Tenhunen


The possibilities to increase single-core performance have ended due to limited instruction-level parallelism and a high penalty when increasing frequency. This prompted designers to move toward multi-core paradigms [1], largely supported by transistor scaling [2]. Scaling down transistor gate length makes it possible to switch them faster at a lower power, as they have a low capacitance. In this context, an important consideration is power density—the power dissipated per unit area. Dennard’s scaling establishes that reducing physical parameters of transistors allows operating them at lower voltage and thus at lower power, because power consumption is proportional to the square of the applied voltage, keeping power density constant [3]. Dennard’s estimation of scaling effects and constant power density is shown in Table 1.1. Theoretically, scaling down further should result in more computational capacity per unit area. However, scaling is reaching its physical limits to an extent that voltage cannot be scaled down as much as transistor gate length leading to failure of Dennardian trend. This along with a rise in leakage current results in increased power density, rather than a constant power density. Higher power density implies more heat generated in a unit area and hence higher chip temperatures which have to be dissipated through cooling solutions, as increase in temperature beyond a certain level results in unreliable functionality, faster aging, and even permanent failure of the chip. To ensure a safe operation, it is essential for the chip to perform within a fixed power budget [4]. In order to avoid too high power dissipation, a certain part of the chip needs to remain inactive; the inactive part is termed dark silicon [5]. Hence, we have to operate working cores in a multi-core system at less than their full capacity, limiting the performance, resource utilization, and efficiency of the system.


Energy Efficiency Threshold Voltage Power Budget Frequency Scaling Technology Node 
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  1. 1.
    H. Sutter, The free lunch is over: a fundamental turn toward concurrency in software. Dr. Dobb’s J. 30 (3), 202–210 (2005)Google Scholar
  2. 2.
    G.E. Moore, Cramming more components onto integrated circuits. Proc. IEEE 86 (1), 82–85 (2002)CrossRefGoogle Scholar
  3. 3.
    R.H. Dennard, V. Rideout, E. Bassous, A. Leblanc, Design of ion-implanted mosfet’s with very small physical dimensions. IEEE J. Solid-State Circuits 9 (5), 256–268 (1974)CrossRefGoogle Scholar
  4. 4.
    M.-H. Haghbayan, A.-M. Rahmani, A.Y. Weldezion, P. Liljeberg, J. Plosila, A. Jantsch, H. Tenhunen, Dark silicon aware power management for manycore systems under dynamic workloads, in Proceedings of IEEE International Conference on Computer Design (2014), pp. 509–512Google Scholar
  5. 5.
    H. Esmaeilzadeh, E. Blem, R.S. Amant, K. Sankaralingam, D. Burger, Dark silicon and the end of multicore scaling, in Proceedings of IEEE International Symposium on Computer Architecture (2011), pp. 365–376Google Scholar
  6. 6.
    J. Kong, S.W. Chung, K. Skadron, Recent thermal management techniques for microprocessors, in ACM Computing Surveys (2012), pp. 13:1–13:42Google Scholar
  7. 7.
    Semiconductor Industry Association, International technology roadmap for semiconductors (ITRS), 2011 edition (2011)Google Scholar
  8. 8.
    H. Esmaeilzadeh, E. Blem, R.S. Amant, K. Sankaralingam, D. Burger, Dark silicon and the end of multicore scaling. IEEE Micro 32 (3), 122–134 (2012)CrossRefGoogle Scholar
  9. 9.
    Semiconductor Industry Association, International technology roadmap for semiconductors (ITRS), 2013 edition (2013)Google Scholar
  10. 10.
    S. Borkar, The exascale challenge, in Proceedings of the VLSI Design Automation and Test (2010)Google Scholar
  11. 11.
    G. Venkatesh, J. Sampson, N. Goulding, S. Garcia, V. Bryksin, J. Lugo-Martinez, S. Swanson, M.B. Taylor, Conservation cores: reducing the energy of mature computations, in ACM SIGARCH Computer Architecture News, vol. 38(1) (2010), pp. 205–218Google Scholar
  12. 12.
    T. Mudge, Power: a first-class architectural design constraint. Computer 34 (4), 52–58 (2001)CrossRefGoogle Scholar
  13. 13.
    S. Borkar, Getting gigascale chips: challenges and opportunities in continuing Moore’s law. Queue 1 (7), 26 (2003)Google Scholar
  14. 14.
    S. Borkar, A.A. Chien, The future of microprocessors. Commun. ACM 54 (5), 67–77 (2011)CrossRefGoogle Scholar
  15. 15.
    H. Sasaki, M. Ono, T. Yoshitomi, T. Ohguro, S.-I. Nakamura, M. Saito, H. Iwai, 1.5 nm direct-tunneling gate oxide Si MOSFET’s. IEEE Trans. Electron Devices 43 (8), 1233–1242 (1996)Google Scholar
  16. 16.
    S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, V. De, Parameter variations and impact on circuits and microarchitecture, in Proceedings of ACM Design Automation Conference (2003), pp. 338–342Google Scholar
  17. 17.
    N.S. Kim, T. Austin, D. Baauw, T. Mudge, K. Flautner, J.S. Hu, M.J. Irwin, M. Kandemir, V. Narayanan, Leakage current: Moore’s law meets static power. IEEE Comput. 36 (12), 68–75 (2003)CrossRefGoogle Scholar
  18. 18.
    A.P. Chandrakasan, W.J. Bowhill, F. Fox, Design of High-Performance Microprocessor Circuits (Wiley-IEEE Press, NJ, USA, 2000)CrossRefGoogle Scholar
  19. 19.
    C.-H. Choi, K.-Y. Nam, Z. Yu, R.W. Dutton, Impact of gate direct tunneling current on circuit performance: a simulation study. IEEE Trans. Electron Devices 48 (12), 2823–2829 (2001)CrossRefGoogle Scholar
  20. 20.
    G. Sery, S. Borkar, V. De, Life is CMOS: why chase the life after? in Proceedings of ACM Design Automation Conference (2002), pp. 78–83Google Scholar
  21. 21.
    Intel Corporation. Intel Xeon Processor - Measuring Processor Power, revision 1.1. White paper, Intel Corporation, April 2011Google Scholar
  22. 22.
    Intel Corporation. Fourth Generation Mobile Processor Family Data Sheet. White paper, Intel Corporation, July 2014Google Scholar
  23. 23.
    AMD. AMD Kaveri APU A10-7800. Available: Accessed 28 Feb 2015 [Online]
  24. 24.
    G.M. Amdahl, Validity of the single processor approach to achieving large scale computing capabilities, in Proceedings of ACM Spring Joint Computer Conference (1967), pp. 483–485Google Scholar
  25. 25.
    G. Venkatesh, J. Sampson, N. Goulding-Hotta, S.K. Venkata, M.B. Taylor, S. Swanson, Qscores: trading dark silicon for scalable energy efficiency with quasi-specific cores, in Proceedings of IEEE/ACM International Symposium on Microarchitecture (2011), pp. 163–174Google Scholar
  26. 26.
    H. Esmaeilzadeh, E. Blem, R.S. Amant, K. Sankaralingam, D. Burger, Power limitations and dark silicon challenge the future of multicore. ACM Trans. Comput. Syst. 30 (3), 11:1–11:27 (2012)Google Scholar
  27. 27.
    Y. Almog, R. Rosner, N. Schwartz, A. Schmorak, Specialized dynamic optimizations for high-performance energy-efficient microarchitecture, in Proceedings of International Symposium on Code Generation and Optimization: Feedback-directed and Runtime Optimization (2004), pp. 137–148Google Scholar
  28. 28.
    K. Khubaib, M.A. Suleman, M. Hashemi, C. Wilkerson, Y.N. Patt, MorphCore: an energy-efficient microarchitecture for high performance ILP and high throughput TLP, in Proceedings of IEEE/ACM International Symposium on Microarchitecture (2012), pp. 305–316Google Scholar
  29. 29.
    G. Semeraro, G. Magklis, R. Balasubramonian, D.H. Albonesi, S. Dwarkadas, M.L. Scott, Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling, in Proceedings of IEEE International Symposium on High-Performance Computer Architecture (2002), pp. 29–40Google Scholar
  30. 30.
    D.M. Brooks, P. Bose, S.E. Schuster, H. Jacobson, P.N. Kudva, A. Buyuktosunoglu, J.-D. Wellman, V. Zyuban, M. Gupta, P.W. Cook, Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors. IEEE Micro 20 (6), 26–44 (2000)CrossRefGoogle Scholar
  31. 31.
    M.B. Taylor, Is dark silicon useful?: harnessing the four horsemen of the coming dark silicon apocalypse, in Proceedings of ACM Design Automation Conference (2012), pp. 1131–1136Google Scholar
  32. 32.
    E.L. de Souza Carvalho, N.L.V. Calazans, F.G. Moraes, Dynamic task mapping for MPSoCs. IEEE Des. Test Comput. 27 (5), 26–35 (2010)CrossRefGoogle Scholar
  33. 33.
    C.-L. Chou, R. Marculescu, Contention-aware application mapping for network-on-chip communication architectures, in Proceedings of IEEE International Conference in Computer Design (2008), pp. 164–169Google Scholar
  34. 34.
    M. Fattah, M. Daneshtalab, P. Liljeberg, J. Plosila, Smart hill climbing for agile dynamic mapping in many-core systems, in Proceedings of IEEE/ACM Design Automation Conference (2013)Google Scholar
  35. 35.
    M. Fattah, P. Liljeberg, J. Plosila, H. Tenhunen, Adjustable contiguity of run-time task allocation in networked many-core systems, in Proceedings of IEEE Asia and South Pacific Design Automation Conference (2014), pp. 349–354Google Scholar
  36. 36.
    J. Srinivasan, S.V. Adve, P. Bose, J.A. Rivers, The case for lifetime reliability-aware microprocessors, in Proceedings of IEEE International Symposium on Computer Architecture (2004), pp. 276–287Google Scholar
  37. 37.
    J. Srinivasan, S. Adve, P. Bose, J. Rivers, The impact of scaling on processor lifetime reliability, in Proceedings of International Conference on Dependable Systems and Networks (2004)Google Scholar

Copyright information

© Springer International Publishing Switzerland 2017

Authors and Affiliations

  • Anil Kanduri
    • 1
    Email author
  • Amir M. Rahmani
    • 1
  • Pasi Liljeberg
    • 1
  • Ahmed Hemani
    • 2
  • Axel Jantsch
    • 3
  • Hannu Tenhunen
    • 2
  1. 1.University of TurkuTurkuFinland
  2. 2.KTH Royal Institute of TechnologyStockholmSweden
  3. 3.TU WienViennaAustria

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