A New Simulation-Based Fault Injection Approach for the Evaluation of Transient Errors in GPGPUs

  • Sarah Azimi
  • Boyang Du
  • Luca SterponeEmail author
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9637)


General Purpose Graphics Processing Units (GPGPUs) are increasingly adopted thanks to their high computational capabilities. GPGPUs are preferable to CPUs for a large range of computationally intensive applications, not necessarily related to computer graphics. Within the high performance computing context, GPGPUs must require a large amount of resources and have plenty execution units. GPGPUs are becoming attractive for safety-critical applications where the phenomenon of transient errors is a major concern. In this paper we propose a novel transient error fault injection simulation methodology for the accurate simulation of GPGPUs applications during the occurrence of transient errors. The developed environment allows to inject transient errors within all the memory area of GPGPUs and into not user-accessible resources such as in streaming processors combinational logic and sequential elements. The capability of the fault injection simulation platform has been evaluated testing three benchmark applications including mitigation approaches. The amount of computational costs and time measured is minimal thus enabling the usage of the developed approach for effective transient errors evaluation.


Fault Injection Soft Error Single Event Transient Streaming Multiprocessor Transient Error 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Sabena, D., Sonza Reorda, M., Sterpone, L., Rech, P., Carro, L.: On the evaluation of soft-errors detection techniques for GPGPUs. In: Proceedings of 8th Design and Test Symposium (IDT), pp. 1–6, December 2013Google Scholar
  2. 2.
    ESA COROT mission documentation (2014).
  3. 3.
  4. 4.
    Sabena, D., Sonza Reorda, M., Sterpone, L., Rech, P., Carro, L.: Evaluating the radiation sensitivity of GPGPU caches: new algorithms and experimental results. Microelectron. Reliab. 54(11), 2621–2628 (2014). ElsevierCrossRefGoogle Scholar
  5. 5.
    Battista Gomez, L., Capello, F., Carro, L., DeBardeleben, N., Fang, B., Gurumurthi, S., Pattabiraman, K., Rech, P., Sonza Reorda, M.: GPGPUs: how to combine high computational power with high reliability. In: Proceedings of IEEE Design, Automation and Test in Europe (DATE), pp. 1–9 (2014)Google Scholar
  6. 6.
    Rech, P., Aguiar, C., Frost, C., Carro, L.: An efficient and experimentally tuned software-based hardening strategy for matrix multiplication on GPUs. IEEE Trans. Nucl. Sci. 60(4), 2797–2804 (2013). Part. 1CrossRefGoogle Scholar
  7. 7.
    Sabena, D., Sterpone, L., Carro, L., Rech, P.: Reliability evaluation of embedded GPGPUs for safety critical applications. IEEE Trans. Nucl. Sci. 61(6), 3123–3129 (2014)CrossRefGoogle Scholar
  8. 8.
    Sabena, D., Sonza Reorda, M., Sterpone, L., Rech, P., Carro, L.: On the evaluation of soft-errors detection techniques for GPGPUs. In: 8th International Design and Test Symposium (IDT 2013), pp. 1–6, 16–18 December 2013Google Scholar
  9. 9.
    Tan, J., Goswami, N., Li, T., Fu, X.: Analyzing soft-error vulnerability on GPGPU microarchitecture. In: 2011 IEEE International Symposium on Workload Characterization (IISWC), pp. 226–235 (2011)Google Scholar
  10. 10.
    Fang, B., Wei, J., Pattabiraman, K., Ripeanu, M.: Towards building error resilient GPGPU applications. In: SC Companion: High Performance Computing, Networking Storage and Analysis (2012)Google Scholar
  11. 11.
    Collange, S., Daumas, M., Defour, D., Parello, D.: Barra: a parallel functional simulator for GPGPU. In: 18th Annual IEEE/ACM International Symposium on Modeling, pp. 351–360 (2010)Google Scholar
  12. 12.
    Bakhoda, A., Yuan, G.L., Fung, W.W.L., Wong, H., Aamodt, T.M.: Analyzing CUDA workloads using a detailed GPU simulator. In: ISPASS (2009)Google Scholar
  13. 13.
    Fung, W.W.L., Sham, I., Yuan, G., Aamodt, T.M.: Dynamic warp formation and scheduling for efficient GPU control flow. In: 40th IEEE/ACM International Simposium on Microarchitecture (2014)Google Scholar
  14. 14.
  15. 15.
    Fang, B., Pattabiraman, K., Ripeanu, M., Gurumurthi, S.: GPU-Qin: a methodology for evaluating the error resilience of GPGPU applications. In: IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 221–230 (2014)Google Scholar
  16. 16.
    Sterpone, L., Du, B., Azimi, S.: Radiation-induced single event transients modeling and testing on nanometric flash-based technology. Microelectron. Reliab. 55(9–10), 2087–2091 (2015)CrossRefGoogle Scholar
  17. 17.
    NVIDIA CUDA programming guide, version 2.3.1, August 2009Google Scholar
  18. 18.
    Andryc, K., Merchant, M., Tessier, R.: FlexGrip: a soft GPGPU for FPGAs. In: International Conference on Field Programmable Technology, Kyoto, Japan, pp. 230–237, December 2013Google Scholar
  19. 19.
    IGLOO, ProASIC3, Smartfusion and Fusion Macro Library Guide for Software 9.0, p. 193, February 2010Google Scholar
  20. 20.
    Olivera, D.A.G., Rech, P., Pilla, L.L., Navaux, P.O.A., Carro, L.: GPGPUs ECC efficiency and efficacy. In: International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 209–215 (2014)Google Scholar

Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  1. 1.Politecnico di TorinoTurinItaly

Personalised recommendations