SystemVerilog Assertions and Functional Coverage pp 207-246 | Cite as
Very Important Topics and Applications
Chapter
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Abstract
Introduction: This chapter addresses many important topics such as Asynchronous FIFO assertions, triggering concurrent assertions from procedural blocks, calling subroutines, sequences as formal arguments, as antecedent and as triggering condition in a sensitivity list.
Keywords
Asynchronous FIFO Procedural code Vacuous pass Sequence Property Sensitivity list Subroutines Antecedent Consequent Action block CyclicCopyright information
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