FPGA Soft-Core Processors, Compiler and Hardware Optimizations Validated Using HOG

  • Colm Kelly
  • Fahad Manzoor Siddiqui
  • Burak Bardak
  • Yun Wu
  • Roger Woods
  • Karren Rafferty
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9625)

Abstract

There is demand for an easily programmable, high performance image processing platform based on FPGAs. In previous work, a novel, high performance processor - IPPro was developed and a Histogram of Orientated Gradients (HOG) algorithm study undertaken on a Xilinx Zynq platform. Here, we identify and explore a number of mapping strategies to improve processing efficiency for soft-cores and a number of options for creation of a division coprocessor. This is demonstrated for the revised high definition HOG implementation on a Zynq platform, resulting in a performance of 328 fps which represents a 146 % speed improvement over the original realization and a tenfold reduction in energy.

Keywords

FPGA Memory Image processing HOG 

References

  1. 1.
    Gat, Y., Kozintsev, I., Nestares, O.: Fusing image data with location and orientation sensor data streams for consumer video applications. In: 2010 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops (CVPRW), pp. 1–8 (2010)Google Scholar
  2. 2.
    Siddiqui, F., Russell, M., Bardak, B., Woods, R., Rafferty, K.: Ippro: FPGA based image processing processor. In: 2014 IEEE Workshop on Signal Processing Systems (SiPS), pp. 1–6 (2014)Google Scholar
  3. 3.
    Andryc, K., Merchant, M., Tessier, R.: Flexgrip: a soft GPGPU for FPGAs. In: 2013 International Conference on Field-Programmable Technology (FPT), pp. 230–237 (2013)Google Scholar
  4. 4.
    Cheah, H.Y., Fahmy, S., Kapre, N.: Analysis and optimization of a deeply pipelined FPGA soft processor. In: 2014 International Conference on Field-Programmable Technology (FPT), pp. 235–238 (2014)Google Scholar
  5. 5.
    Severance, A., Lemieux, G.: Venice: a compact vector processor for FPGA applications. In: 2012 International Conference on Field-Programmable Technology (FPT), pp. 261–268 (2012)Google Scholar
  6. 6.
    Xilinx Inc. San Jose. UG473: 7 Series FPGAs Memory Resources (2014). http://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf
  7. 7.
    Dalal, N., Triggs, B.: Histograms of oriented gradients for human detection. In: IEEE Computer Society Conference on Computer Vision and Pattern Recognition, CVPR 2005, vol. 1, pp. 886–893 (2005)Google Scholar
  8. 8.
    Kelly, C., Siddiqui, F., Bardak, B., Woods, R.: Histogram of oriented gradients front end processing: an FPGA based processor approach. In: 2014 IEEE Workshop on Signal Processing Systems (SiPS), pp. 1–6 (2014)Google Scholar
  9. 9.
    Xilinx Inc. San Jose. DS183: Viretx-7 and XT FPGAs Data Sheet: DC and AC Switching Characteristics, May 2015. http://www.xilinx.com/support/documentation/data_sheets/ds183_Virtex_7_Data_Sheet.pdf
  10. 10.
    Oberman, S., Flynn, M.: Division algorithms and implementations. IEEE Trans. Comput. 46(8), 833–854 (1997)MathSciNetCrossRefGoogle Scholar
  11. 11.
    Sutter, G., Deschamps, J.-P., Bioul, G., Boemo, E.: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. Springer, Berlin (2004)Google Scholar
  12. 12.
    Deschamps, J., Sutter, G., Cantó, E.: Guide to FPGA Implementation of Arithmetic Functions. Lecture Notes in Electrical Engineering. Springer, The Netherlands (2012)CrossRefMATHGoogle Scholar
  13. 13.
    Xilinx Inc. San Jose. LogiCORE IP Divider Generator v3.0 (2011). http://www.xilinx.com/support/documentation/ip_documentation/div_gen_ds530.pdf
  14. 14.
    Hahnle, M., Saxen, F., Hisung, M., Brunsmann, U., Doll, K.: FPGA-based real-time pedestrian detection on high-resolution images. In: 2013 IEEE Conference on Computer Vision and Pattern Recognition Workshops (CVPRW), pp. 629–635 (2013)Google Scholar
  15. 15.
    Ma, X., Najjar, W., Roy-Chowdhury, A.: Evaluation and acceleration of high-throughput fixed-point object detection on FPGAs. IEEE Trans. Circ. Syst. Video Technol. 25(6), 1051–1062 (2015)CrossRefGoogle Scholar
  16. 16.
    Negi, K., Dohi, K., Shibata, Y., Oguri, K.: Deep pipelined one-chip FPGA implementation of a real-time image-based human detection algorithm. In: 2011 International Conference on Field-Programmable Technology (FPT), pp. 1–8 (2011)Google Scholar

Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  • Colm Kelly
    • 1
  • Fahad Manzoor Siddiqui
    • 2
  • Burak Bardak
    • 2
  • Yun Wu
    • 2
  • Roger Woods
    • 2
  • Karren Rafferty
    • 2
  1. 1.ThalesBelfastUK
  2. 2.Queens UniversityBelfastUK

Personalised recommendations