Adaptive Bandwidth Router for 3D Network-on-Chips

  • Stephanie FriederichEmail author
  • Niclas Lehmann
  • Jürgen Becker
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9625)


As system on a chip (SoC) designs continue to head in the direction of miniaturization, with an ever increasing size of components, three-dimensional (3D) integration technologies are used to satisfy performance enhancements. With increasing number of cores, bus based SoC designs do not scale well, hence network on chip (NoC) architectures are introduced to avoid communication bottlenecks. Since two-dimensional NoC designs are not easy to partition across 3D chip layers, we introduce an adaptive 3D NoC architecture. The bandwidth and frequency of inter layer connections can be chosen independently from the router links within a layer. To prevent thermal hot spots in the middle of the chip, memory layers are placed in between compute layers. Supplemental this solves the high demand of our distributed memory architecture.


Field Programmable Gate Array Mesh Network Virtual Channel Input Buffer Torus Network 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



This work was supported by the German Research Foundation (DFG) as part of the Transregional Collaborative Research Center “Invasive Computing” (SFB/TR89).


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Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  • Stephanie Friederich
    • 1
    Email author
  • Niclas Lehmann
    • 1
  • Jürgen Becker
    • 1
  1. 1.Karlsruhe Institute of Technology (KIT)KarlsruheGermany

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