A Dynamic Cache Architecture for Efficient Memory Resource Allocation in Many-Core Systems
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Today’s computing systems still mostly consist of homogeneous multi-core processing systems with statically allocated computing resources. Looking into the future, these computing systems will evolve to heterogeneous processing systems with more diverse processing units and new requirements. With multiple applications running concurrently on these many-core platforms, these applications compete for computational resources and thus processing power. However, not all applications are able to efficiently make use of all available resources at all times, which leads to the challenge to efficiently allocate tasks to computational resources during run-time. This issue is especially crucial when looking at cache resources, where the bandwidth and the available resources strongly bound computation times. For example, streaming based algorithms will run concurrently with block-based computations, which leads to an inefficient allocation of cache resources.
In this paper, we propose a dynamic cache architecture that enables the parameterization and the resource allocation of cache memory resources between cores during run-time. The reallocation is done with only little overhead such that each algorithm class can be more efficiently executed on the many-core platform. We contribute with a cache architecture that is for the first time prototyped on programmable hardware to demonstrate the feasibility of the proposed approach. At last we evaluate the overhead introduced by the increased flexibility of the hardware architecture.
KeywordsDynamic Cache Cache Resources Programmable Hardware Many-core Platforms Account Tile
This research work is supported by the German Research Foundation (DFG) within the Transregio SFB Invasive Computing (DFG SFB/TRR89).
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