Hardware Acceleration of SVM-Based Classifier for Melanoma Images

  • Shereen AfifiEmail author
  • Hamid GholamHosseini
  • Roopak Sinha
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9555)


Melanoma is the most aggressive form of skin cancer which is responsible for the majority of skin cancer related deaths. Recently, image-based Computer Aided Diagnosis (CAD) systems are being increasingly used to help skin cancer specialists in detecting melanoma lesions early, and consequently reduce mortality rates. In this paper, we implement the most compute-intensive classification stage in the CAD onto FPGA, aiming to achieve acceleration of the system for deploying as an embedded device. A hardware/software co-design approach was proposed for implementing the Support Vector Machine (SVM) classifier for classifying melanoma images online in real-time. The hybrid Zynq platform was used for implementing the proposed architecture of the SVM classifier designed using the High Level Synthesis design methodology. The implemented SVM classification system on Zynq demonstrated high performance with low resources utilization and power consumption, meeting several embedded systems constraints.


SVM CAD Melanoma FPGA Hardware implementation 


  1. 1.
    Sathiya, S.B., Kumar, S.S., Prabin, A.: A survey on recent computer-aided diagnosis of melanoma. In: International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT), pp. 1387–1392. IEEE Press (2014)Google Scholar
  2. 2.
    Véstias, M.P.: High-performance reconfigurable computing granularity. In: Encyclopedia of Information Science and Technology, pp. 3558–3567 (2015)Google Scholar
  3. 3.
    Saegusa, T., Maruyama, T., Yamaguchi, Y.: How fast is an FPGA in image processing? In: International Conference on Field Programmable Logic and Applications, FPL 2008 pp. 77–82. IEEE Press (2008)Google Scholar
  4. 4.
    Sabouri, P., GholamHosseini, H., Larsson, T., Collins, J.: A cascade classifier for diagnosis of melanoma in clinical images. In: 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), pp. 6748–6751. IEEE Press (2014)Google Scholar
  5. 5.
    Nayak, J., Naik, B., Behera, H.: A comprehensive survey on support vector machine in data mining tasks: applications & challenges. Int. J. Database Theory Appl. 8, 169–186 (2015)CrossRefGoogle Scholar
  6. 6.
    Patil, R., Gupta, G., Sahula, V., Mandal, A.: Power aware hardware prototyping of multiclass SVM classifier through reconfiguration. In: 2012 25th International Conference on VLSI Design (VLSID), pp. 62–67. IEEE Press (2012)Google Scholar
  7. 7.
    Hussain, H.M., Benkrid, K., Seker, H.: Reconfiguration-based implementation of SVM classifier on FPGA for classifying microarray data. In: Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBS), pp. 3058–3061 (2013)Google Scholar
  8. 8.
    Hussain, H., Benkrid, K., Seker, H.: Novel dynamic partial reconfiguration implementations of the support vector machine classifier on FPGA. Turkish Journal of Electrical Engineering and Computer Sciences (2014)Google Scholar
  9. 9.
    Mandal, B., Sarma, M.P., Sarma, K.K.: Implementation of systolic array based SVM classifier using multiplierless kernel. In: Proceedings of the 16th International Conference on Automatic Control, Modelling & Simulation (ACMOS 2014), pp. 288–294. WSEAS Press (2014)Google Scholar
  10. 10.
    Kyrkou, C., Theocharides, T.: A parallel hardware architecture for real-time object detection with support vector machines. IEEE Trans. Comput. 61, 831–842 (2012)MathSciNetCrossRefzbMATHGoogle Scholar
  11. 11.
    Papadonikolakis, M., Bouganis, C.: Novel cascade FPGA accelerator for support vector machines classification. IEEE Trans. Neural Netw. Learn. Syst. 23, 1040–1052 (2012)CrossRefGoogle Scholar
  12. 12.
    Kyrkou, C., Theocharides, T., Bouganis, C.-S.: An embedded hardware-efficient architecture for real-time cascade support vector machine classification. In: 2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIII), pp. 129–136. IEEE Press (2013)Google Scholar
  13. 13.
    Kyrkou, C., Bouganis, C.-S., Theocharides, T., Polycarpou, M.M.: Embedded hardware-efficient real-time classification with cascade support vector machines. IEEE Trans. Neural Netw. Learn. Syst. 27, 99–112 (2015)MathSciNetCrossRefGoogle Scholar
  14. 14.
    Shuai, X., Yibin, L., Zhiping, J., Lei, J.: Binarization based implementation for real-time human detection. In: 2013 23rd International Conference on Field Programmable Logic and Applications (FPL), pp. 1–4 (2013)Google Scholar
  15. 15.
    Ruiz-Llata, M., Guarnizo, G., Yébenes-Calvino, M.: FPGA implementation of a support vector machine for classification and regression. In: The 2010 International Joint Conference on Neural Networks (IJCNN), pp. 1–5. IEEE Press (2010)Google Scholar
  16. 16.
    Jallad, A.H.M., Mohammed, L.B.: Hardware Support Vector Machine (SVM) for satellite on-board applications. In: 2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pp. 256–261 (2014)Google Scholar
  17. 17.
    Kyrkou, C., Theocharides, T., Bouganis, C.S.: A hardware-efficient architecture for embedded real-time cascaded support vector machines classification. In: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI, pp. 341–342. ACM (2013)Google Scholar
  18. 18.
    Papadonikolakis, M., Bouganis, C.-S.: A novel FPGA-based SVM classifier. In: International Conference on Field-Programmable Technology (FPT), pp. 283–286. IEEE Press (2010)Google Scholar
  19. 19.
    Kim, S., Lee, S., Cho, K.: Design of high-performance unified circuit for linear and non-linear SVM classifications. J. Semicond. Technol. Sci. 12, 162–167 (2012)CrossRefGoogle Scholar
  20. 20.
    Koide, T., Anh-Tuan, H., Okamoto, T., Shigemi, S., Mishima, T., Tamaki, T., Raytchev, B., Kaneda, K., Kominami, Y., Miyaki, R., Matsuo, T., Yoshida, S., Tanaka, S.: FPGA implementation of type identifier for colorectal endoscopie images with NBI magnification. In: 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 651–654 (2014)Google Scholar
  21. 21.
    Ago, Y., Nakano, K., Ito, Y.: A classification processor for a support vector machine with embedded DSP slices and block RAMs in the FPGA. In: 2013 IEEE 7th International Symposium on Embedded Multicore Socs (MCSoC), pp. 91–96 (2013)Google Scholar
  22. 22.
    Mizuno, K., Terachi, Y., Takagi, K., Izumi, S., Kawaguchi, H., Yoshimoto, M.: Architectural study of HOG feature extraction processor for real-time object detection. In: 2012 IEEE Workshop on Signal Processing Systems (SiPS), pp. 197–202 (2012)Google Scholar
  23. 23.
    Komorkiewicz, M., Kluczewski, M., Gorgon, M.: Floating point hog implementation for real-time multiple object detection. In: 2012 22nd International Conference on Field Programmable Logic and Applications (FPL), pp. 711–714. IEEE Press (2012)Google Scholar
  24. 24.
    Liu, C., Qiao, F., Yang, X., Yang, H.: Hardware acceleration with pipelined adder for support vector machine classifier. In: 2014 Fourth International Conference on Digital Information and Communication Technology and it’s Applications (DICTAP), pp. 13–16. IEEE Press (2014)Google Scholar
  25. 25.
    Pietron, M., Wielgosz, M., Zurek, D., Jamro, E., Wiatr, K.: Comparison of GPU and FPGA implementation of SVM algorithm for fast image segmentation. In: Kubátová, H., Hochberger, C., Daněk, M., Sick, B. (eds.) ARCS 2013. LNCS, vol. 7767, pp. 292–302. Springer, Heidelberg (2013)CrossRefGoogle Scholar
  26. 26.
    Kryjak, T., Komorkiewicz, M., Gorgon, M.: FPGA implementation of real-time head-shoulder detection using local binary patterns, SVM and foreground object detection. In: 2012 Conference on Design and Architectures for Signal and Image Processing (DASIP), pp. 1–8 (2012)Google Scholar
  27. 27.
    Qasaimeh, M., Sagahyroon, A., Shanableh, T.: FPGA-based parallel hardware architecture for real-time image classification. IEEE Trans. Comput. Imag. 1, 56–70 (2015)MathSciNetCrossRefGoogle Scholar
  28. 28.
    Kelly, C., Siddiqui, F.M., Bardak, B., Woods, R.: Histogram of oriented gradients front end processing: an FPGA based processor approach. In: 2014 IEEE Workshop on Signal Processing Systems (SiPS), pp. 1–6. IEEE Press (2014)Google Scholar
  29. 29.
  30. 30.
  31. 31.
  32. 32.
    Ning, M., Shaojun, W., Yeyong, P., Yu, P.: Implementation of LS-SVM with HLS on Zynq. In: 2014 International Conference on Field-Programmable Technology (FPT), pp. 346–349. IEEE Press (2014)Google Scholar
  33. 33.
    Joachims, T.: Making large-scale SVM learning practical. In: Schölkopf, B., Burges, C., Smola, A. (eds.) Advances in Kernel Methods: Support Vector Learning. MIT Press, Cambridge (1999)Google Scholar
  34. 34.
    Mahmoodi, D., Soleimani, A., Khosravi, H., Taghizadeh, M.: FPGA simulation of linear and nonlinear support vector machine. J. Softw. Eng. Appl. 4, 320–328 (2011)CrossRefGoogle Scholar
  35. 35.
    Zynq-7000 All Programmable SoC Acccelerator for Floating-Point Matrix Multiplication using Vivado HLS,
  36. 36.
    Qasaimeh, M., Sagahyroon, A., Shanableh, T.: FPGA-based parallel hardware architecture for real-time image classification. IEEE Trans. Comput. Imag. 1, 56–70 (2015)MathSciNetCrossRefGoogle Scholar

Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  • Shereen Afifi
    • 1
    Email author
  • Hamid GholamHosseini
    • 1
  • Roopak Sinha
    • 2
  1. 1.Department of Electrical and Electronics Engineering, School of EngineeringAuckland University of TechnologyAucklandNew Zealand
  2. 2.School of Computer and Mathematical SciencesAuckland University of TechnologyAucklandNew Zealand

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