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Model Checking of UML Activity Diagrams Using a Rule-Based Logical Model

  • Iwona GrobelnaEmail author
  • Michał Grobelny
  • Marian Adamski
Chapter
Part of the Studies in Systems, Decision and Control book series (SSDC, volume 45)

Abstract

UML activity diagrams can be used as semi-formal specification of logic controller behavior. On the other hand, formal methods applied at any stage of system development allow increasing in the quality of final products. In the chapter use of the model checking technique to validate the specification against some specified requirements is described. The specification is initially expressed by means of UML activity diagrams and then is transformed to a rule-based logical model suitable both for verification purposes and for logical synthesis for FPGA devices.

Keywords

Activity diagrams Formal methods Logic controller Model checking Specification Verification UML 

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Copyright information

© Springer International Publishing Switzerland 2016

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 2.5 International License (http://creativecommons.org/licenses/by-nc/2.5/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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Authors and Affiliations

  • Iwona Grobelna
    • 1
    Email author
  • Michał Grobelny
    • 2
  • Marian Adamski
    • 3
  1. 1.Institute of Electrical EngineeringUniversity of Zielona GóraZielona GóraPoland
  2. 2.Department of Media and Information TechnologiesUniversity of Zielona GóraZielona GóraPoland
  3. 3.Institute of Metrology, Electronics and Computer ScienceUniversity of Zielona GóraZielona GóraPoland

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