Chapter

FPGAs for Software Programmers

pp 115-136

Date:

Big Data and HPC Acceleration with Vivado HLS

  • Moritz SchmidAffiliated withFriedrich-Alexander-Universität Erlangen-Nürnberg (FAU) Email author 
  • , Christian SchmittAffiliated withFriedrich-Alexander-Universität Erlangen-Nürnberg (FAU)
  • , Frank HannigAffiliated withFriedrich-Alexander-Universität Erlangen-Nürnberg (FAU)
  • , Gorker Alp MalazgirtAffiliated withBogazici University
  • , Nehir SonmezAffiliated withBarcelona Supercomputing CenterCentro Superior de Investigaciones Cientificas (IIIA-CSIC)Universitat Politecnica de Catalunya
  • , Arda YurdakulAffiliated withBogazici University
  • , Adrian CristalAffiliated withBarcelona Supercomputing CenterCentro Superior de Investigaciones Cientificas (IIIA-CSIC)Universitat Politecnica de Catalunya

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Abstract

Recent years have seen a new generation of HLS tools, which do not only allow to generate hardware architectures from hardware behavioral models, but perform synthesis starting from algorithms specified in HLLs. One of the reasons for this development is the ever growing popularity of reconfigurable logic, which aims at providing the performance and energy efficiency of integrated circuits at a flexibility that is very close to software.