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FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction

  • Andrew BeckerEmail author
  • Djordje Maksimovic
  • David Novo
  • Mohsen Ewaida
  • Andreas Veneris
  • Barbara Jobstmann
  • Paolo Ienne
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9434)

Abstract

Functional verification occupies a significant amount of the digital circuit design cycle. In this paper, we present a novel approach to improve circuit debugging which not only localizes errors with high confidence, but can also provide semantically-meaningful source code corrections. Our method, which we call FudgeFactor, starts with a buggy design, at least one failing and several correct test vectors, and a list of suspect bug locations. We obtain the suspect location from a state-of-the-art debugging tool that includes a significant number of false positives. Using this list and a library of rules empirically characterizing typical source-code mistakes, we instrument the buggy design to allow each potential error location to either be left unchanged, or replaced with a set of possible corrections. FudgeFactor then combines the instrumented design with the test vectors and solves a 2QBF-SAT problem to find the minimum number of source-level changes from the original code which correct the bug. Our 13 benchmarks demonstrate that our method is able to correct a sizable portion of realistic bugs within a reasonable computational time. With the aid of available golden reference designs, we show that those corrections are, at least on these benchmarks, always valid and non-trivial fixes. We believe that our technique significantly improves over other debugging tools in two respects: When we succeed, we obtain a much more precise bug localization with no false positives and little or no ambiguity. Additionally, we offer bug corrections that are inherently meaningful to the designers and enable designers to quickly recognize and understand the root cause of the bug with a high level of confidence.

Keywords

Error Localization Free Variable Rule Transformer Advance Encryption Standard Test Vector 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Alizadeh, B., Behnam, P., Sadeghi-Kohan, S.: A scalable formal debugging approach with auto-correction capability based on static slicing and dynamic ranking for RTL datapath designs. IEEE Trans. Comput. 64(6), 1564–1578 (2015)MathSciNetGoogle Scholar
  2. 2.
    Alur, R., Bodik, R., Juniwal, G., Martin, M.M.K., Raghothaman, M., Seshia, S.A., Singh, R., Solar-Lezama, A., Torlak, E., Udupa, A.: Syntax-guided synthesis. In: Proceedings of the 13th Conference on Formal Methods in Computer-Aided Design, Portland, OR, pp. 1–8, October 2013Google Scholar
  3. 3.
    Bloem, R., Wotawa, F.: Verification and fault localization in VHDL programs. J. Telematics Eng. Soc. 2, 30–33 (2002)Google Scholar
  4. 4.
    Chang, K.H., Markov, I., Bertacco, V.: Fixing design errors with counterexamples and resynthesis. In: Proceedings of the Asia and South Pacific Design Automation Conference, Yokohama, Japan, pp. 944–949, January 2007Google Scholar
  5. 5.
    Chang, K.H., Wagner, I., Bertacco, V., Markov, I.: Automatic error diagnosis and correction for RTL designs. In: Proceedings of the High Level Design Validation and Test Workshop, Irvine, CA, pp. 65–72, November 2007Google Scholar
  6. 6.
    Chung, P.Y., Hajj, I.N.: ACCORD: Automatic catching and correction of logic design errors in combinational circuits. In: Proceedings of the International Test Conference, Baltimore, MD, pp. 742–751, September 1992Google Scholar
  7. 7.
    Chung, P.Y., Wang, Y.M., Hajj, I.N.: Logic design error diagnosis and correction. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2(3), 320–332 (1994)CrossRefGoogle Scholar
  8. 8.
    Debroy, V., Wong, W.E.: Using mutation to automatically suggest fixes for faulty programs. In: Proceedings of the Third International Conference on Software Testing, Verification and Validation, pp. 65–74, April 2010Google Scholar
  9. 9.
    Foster, H.: Trends in functional verification: a 2014 industry study. In: 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 1–6, June 2015Google Scholar
  10. 10.
    Jobstmann, B., Griesmayer, A., Bloem, R.: Program repair as a game. In: Etessami, K., Rajamani, S.K. (eds.) CAV 2005. LNCS, vol. 3576, pp. 226–238. Springer, Heidelberg (2005) CrossRefGoogle Scholar
  11. 11.
    Mahler, J.: A MIPS CPU written in Verilog. https://github.com/jmahler/mips-cpu. Accessed 24 April 2015
  12. 12.
    OpenCores: Opencores database. http://www.opencores.org
  13. 13.
    Peischl, B., Wotawa, F.: Automated source level error localization in hardware designs. J. IEEE Des. Test Comput. 23(1), 8–19 (2006)CrossRefGoogle Scholar
  14. 14.
    Singh, R., Gulwani, S., Solar-Lezama, A.: Automated feedback generation for introductory programming assignments. In: Proceedings of the 34th ACM SIGPLAN Conference on Programming Language Design and Implementation, Seattle, WA, pp. 15–26, June 2013Google Scholar
  15. 15.
    Smith, A., Veneris, A., Ali, M.F., Viglas, A.: Fault diagnosis and logic debugging using Boolean satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. CAD 24(10), 1606–1621 (2005)CrossRefGoogle Scholar
  16. 16.
    Lezama, A.S.: Program synthesis by sketching. Ph.D. thesis, UC Berkeley, December 2008. http://eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-177.html
  17. 17.
    Staber, S., Jobstmann, B., Bloem, R.: Finding and fixing faults. J. Comput. Syst. Sci. 78(2), 441–460 (2012)zbMATHMathSciNetCrossRefGoogle Scholar
  18. 18.
    Wolf, C., Glaser, J., Kepler, J.: Yosys - a free Verilog synthesis suite. In: Proceedings of 21st Austrian Workshop on Microelectronics, Linz, Austria, October 2013Google Scholar

Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  • Andrew Becker
    • 1
    Email author
  • Djordje Maksimovic
    • 2
  • David Novo
    • 1
  • Mohsen Ewaida
    • 1
  • Andreas Veneris
    • 2
  • Barbara Jobstmann
    • 1
  • Paolo Ienne
    • 1
  1. 1.Ecole Polytechnique Fédérale de LausanneLausanneSwitzerland
  2. 2.University of TorontoTorontoCanada

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