Haifa Verification Conference

Hardware and Software: Verification and Testing pp 173-189 | Cite as

Quasi-equal Clock Reduction: Eliminating Assumptions on Networks

Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9434)

Abstract

Quasi-equal clock reduction for networks of timed automata replaces clocks in equivalence classes by representative clocks. An existing approach which reduces quasi-equal clocks and does not constrain the support of properties of networks, yields significant reductions of the overall verification time of properties. However, this approach requires strong assumptions on networks in order to soundly apply the reduction of clocks. In this work we propose a transformation which does not require assumptions on networks, and does not constrain the support of properties of networks. We demonstrate that the cost of verifying properties is much lower in transformed networks than in their original counterparts with quasi-equal clocks.

References

  1. 1.
    Alur, R., Dill, D.: A theory of timed automata. TCS 126(2), 183–235 (1994)MATHMathSciNetCrossRefGoogle Scholar
  2. 2.
    Herrera, C., Westphal, B., Feo-Arenis, S., Muñiz, M., Podelski, A.: Reducing quasi-equal clocks in networks of timed automata. In: Jurdziński, M., Ničković, D. (eds.) FORMATS 2012. LNCS, vol. 7595, pp. 155–170. Springer, Heidelberg (2012) CrossRefGoogle Scholar
  3. 3.
    Rappaport, T.S.: Wireless communications, vol. 2. Prentice Hall (2002)Google Scholar
  4. 4.
    Behrmann, G., David, A., Larsen, K.G.: A tutorial on uppaal. In: Bernardo, M., Corradini, F. (eds.) SFM-RT 2004. LNCS, vol. 3185, pp. 200–236. Springer, Heidelberg (2004) CrossRefGoogle Scholar
  5. 5.
    Herrera, C., Westphal, B., Podelski, A.: Quasi-equal clock reduction: more networks, more queries. In: Ábrahám, E., Havelund, K. (eds.) TACAS 2014 (ETAPS). LNCS, vol. 8413, pp. 295–309. Springer, Heidelberg (2014) CrossRefGoogle Scholar
  6. 6.
    Bengtsson, J.E., Yi, W.: Timed automata: semantics, algorithms and tools. In: Desel, J., Reisig, W., Rozenberg, G. (eds.) Lectures on Concurrency and Petri Nets. LNCS, vol. 3098, pp. 87–124. Springer, Heidelberg (2004) CrossRefGoogle Scholar
  7. 7.
    Petalidis, N.: Verification of a fieldbus scheduling protocol using timed automata. CI 28(5), 655–672 (2009)Google Scholar
  8. 8.
    Godary, K.: Validation temporelle de réseaux embarqués critiques et fiables pour l’automobile. PhD thesis, Institut National des Sciences Appliquées de Lyon, France (2004)Google Scholar
  9. 9.
    Bérard, B., Bouyer, P., Petit, A.: Analysing the PGM Protocol with UPPAAL. IJPR 42(14), 2773–2791 (2004)CrossRefGoogle Scholar
  10. 10.
    Daws, C., Yovine, S.: Reducing the number of clock variables of timed automata. In: RTSS, pp. 73–81. IEEE (1996)Google Scholar
  11. 11.
    Daws, C., Tripakis, S.: Model checking of real-time reachability properties using abstractions. In: Steffen, B. (ed.) TACAS 1998. LNCS, vol. 1384, pp. 313–329. Springer, Heidelberg (1998) CrossRefGoogle Scholar
  12. 12.
    Braberman, V., Garbervestky, D., Kicillof, N., Monteverde, D., Olivero, A.: Speeding up model checking of timed-models by combining scenario specialization and live component analysis. In: Ouaknine, J., Vaandrager, F.W. (eds.) FORMATS 2009. LNCS, vol. 5813, pp. 58–72. Springer, Heidelberg (2009) CrossRefGoogle Scholar
  13. 13.
    Braberman, V.A., Garbervetsky, D., Olivero, A.: Improving the verification of timed systems using influence information. In: Katoen, J.-P., Stevens, P. (eds.) TACAS 2002. LNCS, vol. 2280, p. 21. Springer, Heidelberg (2002) CrossRefGoogle Scholar
  14. 14.
    Limal, S., Potier, S., Denis, B., Lesage, J.: Formal verification of redundant media extension of ethernet powerlink. In: ETFA, pp. 1045–1052. IEEE (2007)Google Scholar
  15. 15.
    Muñiz, M., Westphal, B., Podelski, A.: Timed automata with disjoint activity. In: Jurdziński, M., Ničković, D. (eds.) FORMATS 2012. LNCS, vol. 7595, pp. 188–203. Springer, Heidelberg (2012) CrossRefGoogle Scholar
  16. 16.
    Muñiz, M., Westphal, B., Podelski, A.: Detecting quasi-equal clocks in timed automata. In: Braberman, V., Fribourg, L. (eds.) FORMATS 2013. LNCS, vol. 8053, pp. 198–212. Springer, Heidelberg (2013) CrossRefGoogle Scholar
  17. 17.
    Olderog, E.-R., Dierks, H.: Real-time systems - formal specification and automatic verification. Cambridge University Press (2008)Google Scholar
  18. 18.
    Dietsch, D., Feo-Arenis, S., et al.: Disambiguation of industrial standards through formalization and graphical languages. In: RE, pp. 265–270. IEEE (2011)Google Scholar
  19. 19.
    Gobriel, S., Khattab, S., Mossé, D., et al.: RideSharing: fault tolerant aggregation in sensor networks using corrective actions. In: SECON, pp. 595–604. IEEE (2006)Google Scholar
  20. 20.
    Jensen, H., Larsen, K., Skou, A.: Modelling and analysis of a collision avoidance protocol using SPIN and Uppaal. In: 2nd SPIN Workshop (1996)Google Scholar
  21. 21.
    Steiner, W., Elmenreich, W.: Automatic recovery of the TTP/A sensor/actuator network. In: WISES, pp. 25–37. Vienna University of Technology (2003)Google Scholar
  22. 22.
    Kordy, P., Langerak, R., et al.: Re-verification of a lip synchronization protocol using robust reachability. In: FMA. EPTCS, vol. 20, pp. 49–62 (2009)Google Scholar

Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  1. 1.Albert-Ludwigs-Universität FreiburgFreiburgGermany

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