DSVerifier: A Bounded Model Checking Tool for Digital Systems

  • Hussama I. Ismail
  • Iury V. Bessa
  • Lucas C. Cordeiro
  • Eddie B. de Lima Filho
  • João E. Chaves Filho
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9232)


This work presents the Digital-Systems Verifier (DSVerifier), which is a verification tool developed for digital systems. In particular, DSVerifier employs the bounded model checking technique based on satisfiability modulo theories (SMT) solvers, which allows engineers to verify the occurrence of design errors, due to the finite word-length approach employed in fixed-point digital filters and controllers. This tool consists in an additional module for the efficient SMT-based context-bounded model checker and presents command-line and graphical user interface (GUI) versions. Indeed, the GUI version is essential for reporting property violations, together with associated counterexamples. DSVerifier is implemented in C/C\(++\) and uses JavaFX for providing GUI support.


  1. 1.
    Jackson, M.: The world and the machine. In: ICSE, pp. 283–292 (1995)Google Scholar
  2. 2.
    Alur, R., et al.: Model-checking for real-time systems. In: LICS, pp. 414–425 (1990)Google Scholar
  3. 3.
    Alur, R., et al.: Model-checking in dense real-time. IC 104(1), 2–34 (1993)zbMATHMathSciNetGoogle Scholar
  4. 4.
    Behrmann, G., David, A., Larsen, K.G.: A tutorial on Uppaal. In: Bernardo, M., Corradini, F. (eds.) SFM-RT 2004. LNCS, vol. 3185, pp. 200–236. Springer, Heidelberg (2004) CrossRefGoogle Scholar
  5. 5.
    Tripakis, S., et al.: Checking timed Buechi automata emptiness efficiently. FMSD 26, 267–292 (2005)zbMATHGoogle Scholar
  6. 6.
    Magellan, Hybrid RTL formal verification. Accessed 12 September 2014
  7. 7.
    Davis, T.A., Sigmon, K.: MATLAB Primer, 7th edn. CRC Press, Boca Raton (2005) Google Scholar
  8. 8.
    Abreu, F.N., et al.: Verifying fixed-point digital filters using SMT-based bounded model checking. SBrT (2013). doi: 10.14209/sbrt.2013.57
  9. 9.
    Bessa, I., et al.: SMT-based bounded model checking of fixed-point digital controllers. In: IECON, pp. 295–301 (2014)Google Scholar
  10. 10.
    Bessa, I., et al.: Verification of delta form realization in fixed-point digital controllers using bounded model checking. In: SBESC, pp. 49–54 (2014)Google Scholar
  11. 11.
    Cordeiro, L., et al.: SMT-based bounded model checking for embedded ANSI-C software. TSE 38(4), 957–974 (2012)Google Scholar
  12. 12.
    Beyer, D.: Software verification and verifiable witnesses. In: Baier, C., Tinelli, C. (eds.) TACAS 2015. LNCS, vol. 9035, pp. 401–416. Springer, Heidelberg (2015) Google Scholar
  13. 13.
    Ogata, K.: Discrete-Time Control Systems. Prentice Hall International editions, Prentice-Hall International, Upper Saddle River (1995) Google Scholar
  14. 14.
    Platzer, A.: Logic and compositional verification of hybrid systems. In: Gopalakrishnan, G., Qadeer, S. (eds.) CAV 2011. LNCS, vol. 6806, pp. 28–43. Springer, Heidelberg (2011) CrossRefGoogle Scholar

Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  • Hussama I. Ismail
    • 1
  • Iury V. Bessa
    • 1
  • Lucas C. Cordeiro
    • 1
  • Eddie B. de Lima Filho
    • 1
  • João E. Chaves Filho
    • 1
  1. 1.Electronic and Information Research CenterFederal University of AmazonasManausBrazil

Personalised recommendations