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Networks of Memristors and Memristive Components

  • Ioannis VourkasEmail author
  • Georgios Ch. Sirakoulis
Chapter
Part of the Emergence, Complexity and Computation book series (ECC, volume 19)

Abstract

Memristors demonstrate a natural basis for computation that combines information processing and storage in the memory itself. A very powerful and promising memristor-based computing structure, which implements analog parallel computations, is the memristor network. In such structure there is continuous information exchange during calculations which renders a tremendous increase of computational power due to the massively parallel network dynamics. In this chapter we explore this computing concept via numerical and circuit simulations for the purpose of investigating the network dynamics, utilizing the well-documented physics of single devices and known network topologies. We address two of the probably most well-known inherently complex problems, in terms of computation time, i.e. the shortest path and the maze-solving problems, via computations in memristor networks. For these specific problems we further extend already proposed memristor network-based computing approaches by introducing certain modifications in the computing platform. Several scenarios are examined considering also the inclusion of devices with different switching characteristics in the same computation. Additionally, we address the appropriate mapping issue of graph-based computational problems via a novel modeling approach, which is based on specific circuit models describing several types of edges connecting the graph vertices. The emergence of new functionalities opens doors to exciting new computing concepts and encourages the development of parallel memristive computing systems.

Keywords

Short Path Destination Node Cellular Automaton High Resistive State Switching Characteristic 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    E.A. Vittoz, Future of analog in the VLSI environment, in IEEE Int. Symp. Circuits Syst. (ISCAS), New Orleans, LA, USA (1990)Google Scholar
  2. 2.
    E. Linn, R. Rosezin, S. Tappertzhofen, U. Bottger, R. Waser, Beyond von Neumann-logic operations in passive crossbar arrays alongside memory operations, Nanotechnology 23, 305205 (2012)Google Scholar
  3. 3.
    D. Stathis, I. Vourkas, G.C. Sirakoulis, Solving AI problems with memristors: a case study for optimal “bin packing”, in 18th Panhellenic Conference on Informatics (PCI), Athens, Greece (2014)Google Scholar
  4. 4.
    D.B. Strukov, G.S. Snider, D.R. Stewart, R.S. Williams, The missing memristor found. Nature 453, 80–83 (2008)CrossRefGoogle Scholar
  5. 5.
    K.H. Kim, S. Gaba, D. Wheeler, J.M. Cruz-Albrecht, T. Hussain, N. Srinivasa, W. Lu, A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications. Nano Lett. 12(1), 389–395 (2012)CrossRefGoogle Scholar
  6. 6.
    H. Kim, M.P. Sah, C. Yang, T. Roska, L.O. Chua, Neural synaptic weighting with a pulse-based memristor circuit. IEEE Trans. Circ. Syst. I Reg. Papers 59(1), 148–158 (2012)MathSciNetCrossRefGoogle Scholar
  7. 7.
    M. Di Ventra, Y.V. Pershin, The parallel approach. Nat. Phys. 9, 200–202 (2013)CrossRefGoogle Scholar
  8. 8.
    M. Di Ventra, Y.V. Pershin, L.O. Chua, Circuit elements with memory: memristors, memcapacitors and meminductors. IEEE Proc. 97(10), 1717–1724 (2009)CrossRefGoogle Scholar
  9. 9.
    J.J. Yang, D.B. Strukov, D.R. Stewart, Memristive devices for computing. Nat. Nano. 8, 13–24 (2013)CrossRefGoogle Scholar
  10. 10.
    Y.V. Pershin, M. Di Ventra, Solving mazes with memristors: a massively parallel approach. Phys. Rev. E 84, 046703 (2011)CrossRefGoogle Scholar
  11. 11.
    Y.V. Pershin, M. Di Ventra, Self-organization and solution of shortest-path optimization problems with memristive networks. Phys. Rev. E 88, 013305 (2013)CrossRefGoogle Scholar
  12. 12.
    Y. Pershin, V. Slipko, M. Di Ventra, Complex dynamics and scale invariance of one-dimensional memristive networks, Phys. Rev. E 87, 022116 (2013)Google Scholar
  13. 13.
    I. Vourkas, G.C. Sirakoulis, Study of memristive elements networks. J. Nano Res. 27, 5–14 (2014)CrossRefGoogle Scholar
  14. 14.
    I. Vourkas, G.C. Sirakoulis, A novel design and modeling paradigm for memristor-based crossbar circuits. IEEE Trans. Nanotechnol. 11(6), 1151–1159 (2012)CrossRefGoogle Scholar
  15. 15.
    J. Borghetti, G.S. Snider, P.J. Kuekes, J.J. Yang, D.R. Stewart, R.S. Williams, Memristive switches enable ‘stateful’ logic operations via material implication. Nature 464(7290), 873–876 (2010)CrossRefGoogle Scholar
  16. 16.
    E. Lehtonen, J.H. Poikonen, M. Laiho, Implication logic synthesis methods for memristors, in IEEE Int. Symp. Circuits Syst. (ISCAS), Seoul, South Korea (2012)Google Scholar
  17. 17.
    S. Kvatinsky, N. Wald, G. Satat, A. Kolodny, U.C. Weiser, E.G. Friedman, MRL—memristor ratioed logic, in 13th International Workshop on Cellular Nanoscale Networks and their Applicarions (CNNA), Turin, Italy (2012)Google Scholar
  18. 18.
    G. Papandroulidakis, I. Vourkas, N. Vasileiadis, G.C. Sirakoulis, Boolean logic operations and computing circuits based on memristors. IEEE Trans. Circuits Syst. II Expr. Briefs 61(12), 972–976 (2014)CrossRefGoogle Scholar
  19. 19.
    S. Kvatinsky, D. Belousov, S. Liman, G. Satat, N. Wald, E.G. Friedman, A. Kolodny, U.C. Weiser, MAGIC—Memristor Aided LoGIC. IEEE Trans. Circuits Syst. II Expr. Briefs 61(11), 895–899 (2014)Google Scholar
  20. 20.
    E. Lehtonen, M. Laiho, CNN using memristors for neighborhood connections, in 12th Internationl Workshop on Cellular Nanoscale Networks and their Applications (CNNA), Berkeley, CA (2010)Google Scholar
  21. 21.
    D. Stathis, I. Vourkas, G.C. Sirakoulis, Shortest Path Computing using Memristor-based Circuits and Cellular Automata, in 11th International Conference on Cellular Automata for Research and Industry (ACRI), Krakow, Poland (2014)Google Scholar
  22. 22.
    Y.V. Pershin, M. Di Ventra, Neuromorphic, digital and quantum computation with memory circuit elements. Proc. IEEE 100(6), 2071–2080 (2012)CrossRefGoogle Scholar
  23. 23.
    W. Zhao, D. Querlioz, J.O. Klein, D. Chabi, C. Chappert, Nanodevice-based novel computing paradigms and the neuromorphic approach, in IEEE Int. Symp. Circuits Syst. (ISCAS), Seoul, South Korea (2012)Google Scholar
  24. 24.
    E. Neftci, J. Binas, U. Rutishauser, E. Chicca, G. Indiveri, R.J. Douglas, Synthesizing cognition in neuromorphic electronic systems, Proc. Nat. Acad. Sci. (PNAS), 110(37), E3468–E3476 (2013)Google Scholar
  25. 25.
    B.V. Benjamin, P. Gao, E. McQuinn, S. Choudhary, A.R. Chandrasekaran, J.-M. Bussat, R. Alvarez-Icaza, J.V. Arthur, P.A. Merolla, K. Boahen, Neurogrid: a mixed-analog-digital multichip system for large-scale neural simulations. IEEE Proc. 102(5), 699–716 (2014)CrossRefGoogle Scholar
  26. 26.
    A. Basu, S. Ramakrishnan, C. Petre, S. Koziol, S. Brink, P.E. Hasler, Neural dynamics in reconfigurable silicon. IEEE Trans. Biomed. Circ. Syst. 4(5), 311–319 (2010)CrossRefGoogle Scholar
  27. 27.
    S. Koziol, S. Brink, J. Hasler, A neuromorphic approach to path planning using a reconfigurable neuron array IC. IEEE Trans. VLSI Syst. 22(12), 2724–2737 (2014)CrossRefGoogle Scholar
  28. 28.
    S. Brink, S. Nease, P. Hasler, S. Ramakrishnan, R. Wunderlich, A. Basu, B. Degnan, A learning-enabled neuron array IC based upon transistor channel models of biological phenomena. IEEE Trans. Biomed. Circ. Syst. 7(1), 71–81 (2013)CrossRefGoogle Scholar
  29. 29.
    C.K.K. Lim, T. Prodromakis, computing motion with 3D memristive grid. arXiv:1303.3067Google Scholar
  30. 30.
    F. Jiang and B.E. Shi, The memristive grid outperforms the resistive grid for edge preserving smoothing, in European Conference on Circuit Theory and Design (ECCTD), Antalya, Turkey (2009)Google Scholar
  31. 31.
    C. Nakagaki, H. Yamada, A. Toth, Maze-solving by an amoeboid organism, Nature 407(470), 6803 (2000)Google Scholar
  32. 32.
    I. Vourkas, D. Stathis, G.C. Sirakoulis, Massively parallel analog computing: Ariadne’s thread was made of memristors. IEEE Trans. Emerg. Top. Comput. (2015, in press). doi:  10.1109/TETC.2015.2420353
  33. 33.
    G. Ligang, F. Alibart, D.B. Strukov, Programmable CMOS/memristor threshold logic. IEEE Trans. Nanotechnol. 12(2), 115–119 (2013)CrossRefGoogle Scholar
  34. 34.
    I. Vourkas, G.C. Sirakoulis, On the generalization of composite memristive network structures for computational analog/digital circuits and systems. Microelectron. J. 45(11), 1380–1391 (2014)CrossRefGoogle Scholar
  35. 35.
    I. Vourkas, G.C. Sirakoulis, On the analog computational characteristics of memristive networks, in 20th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Abu Dhabi (2013)Google Scholar
  36. 36.
    Easy Java Simulations (EJS). Available: http://fem.um.es/Ejs/. Accessed 2014
  37. 37.
    I. Vourkas, D. Stathis, G.C. Sirakoulis, XbarSim: an educational simulation tool for memristive crossbar-based circuits, in IEEE Int. Symp. Circuits Syst. (ISCAS), Lisbon, Portugal (2015)Google Scholar
  38. 38.
    I. Vourkas, A. Batsos, G.C. Sirakoulis, SPICE modeling of nonlinear memristive behavior. Int. J. Circ. Theor. Appl. 43, 553–565 (2015)Google Scholar
  39. 39.
    M.D. Pickett, D.B. Strukov, J.L. Borghetti, J.J. Yang, G.S. Snider, D.R. Stewart, R.S. Williams, Switching dynamics in titanium dioxide memristive devices. J. Appl. Phys. 106, 074508 (2009)CrossRefGoogle Scholar
  40. 40.
    A.I. Adamatzky, Computation of shortest path in cellular automata. Math. Comput. Model. 23(4), 105–113 (1996)MathSciNetCrossRefzbMATHGoogle Scholar
  41. 41.
    K. Ioannidis, G.C. Sirakoulis, I. Andreadis, A path planning method based on cellular automata for cooperative robots. Appl. Artif. Intell. 25(8), 721–745 (2011)CrossRefGoogle Scholar
  42. 42.
    S. Golzari, M.R. Meybodi, A maze routing algorithm based on two dimensional cellular automata, in 7th International Conference on Cellular Automata for Research and Industry (ACRI), Perpignan, France (2006)Google Scholar
  43. 43.
    I. Vourkas, G.C. Sirakoulis, FPGA based cellular automata for environmental modeling, in 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Seville, Spain (2012)Google Scholar
  44. 44.
    A.C. Torrezan, J.P. Strachan, G. Medeiros-Ribeiro, R.S. Williams, Sub-nanosecond switching of a tantalum oxide memristor. Nanotechnology 22(48), 485203 (2011)CrossRefGoogle Scholar
  45. 45.
    C. Sánchez-López, J. Mendoza-López, M.A. Carrasco-Aguilar, A floating analog memristor emulator circuit. IEEE Trans. Circuits Syst. II Expr. Briefs 61(5), 309–313 (2014)CrossRefGoogle Scholar
  46. 46.
    S. Russell, P. Norvig, Artificial Intelligence: A Modern Approach (Prentice-Hall, Englewood Cliffs, NJ, 2003)zbMATHGoogle Scholar

Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  1. 1.Department of Electrical and Computer EngineeringDemocritus University of ThraceXanthiGreece

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