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Reverse Product-Scanning Multiplication and Squaring on 8-Bit AVR Processors

  • Zhe LiuEmail author
  • Hwajeong Seo
  • Johann Großschädl
  • Howon Kim
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8958)

Abstract

High performance, small code size, and good scalability are important requirements for software implementations of multi-precision arithmetic algorithms to fit resource-limited embedded systems. In this paper, we describe optimization techniques to speed up multi-precision multiplication and squaring on the AVR ATmega series of 8-bit microcontrollers. First, we present a new approach to perform multi-precision multiplication, called Reverse Product Scanning (RPS), that resembles the hybrid technique of Gura et al., but calculates the byte-products in the inner loop in reverse order. The RPS method processes four bytes of the two operands in each iteration of the inner loop and employs two carry-catcher registers to minimize the number of add instructions. We also describe an optimized algorithm for multi-precision squaring based on the RPS technique that is, depending on the operand length, up to 44.3 % faster than multiplication. Our AVR Assembly implementations of RPS multiplication and RPS squaring occupy less than 1 kB of code space each and are written in a parameterized fashion so that they can support operands of varying length without recompilation. Despite this high level of flexibility, our RPS multiplication outperforms the looped variant of Hutter et al.’s operand-caching technique and saves between 40 and 51 % of code size. We also combine our RPS multiplication and squaring routines with Karatsuba’s method to further reduce execution time. When executed on an ATmega128 processor, the “karatsubarized RPS method” needs only 85 k clock cycles for a 1024-bit multiplication (or 48 k cycles for a squaring). These results show that it is possible to achieve high performance without sacrificing code size or scalability.

Keywords

Clock Cycle Partial Product Flash Memory Nest Loop Code Size 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  • Zhe Liu
    • 1
    Email author
  • Hwajeong Seo
    • 2
  • Johann Großschädl
    • 1
  • Howon Kim
    • 2
  1. 1.Laboratory of Algorithmics, Cryptology and Security (LACS)University of LuxembourgLuxembourgLuxembourg
  2. 2.School of Computer Science and EngineeringPusan National UniversityBusanRepublic of Korea

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