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Modular Deductive Verification of Multiprocessor Hardware Designs

  • Muralidaran Vijayaraghavan
  • Adam Chlipala
  • Arvind
  • Nirav Dave
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9207)

Abstract

We present a new framework for modular verification of hardware designs in the style of the Bluespec language. That is, we formalize the idea of components in a hardware design, with well-defined input and output channels; and we show how to specify and verify components individually, with machine-checked proofs in the Coq proof assistant. As a demonstration, we verify a fairly realistic implementation of a multicore shared-memory system with two types of components: memory system and processor. Both components include nontrivial optimizations, with the memory system employing an arbitrary hierarchy of cache nodes that communicate with each other concurrently, and with the processor doing speculative execution of many concurrent read operations. Nonetheless, we prove that the combined system implements sequential consistency. To our knowledge, our memory-system proof is the first machine verification of a cache-coherence protocol parameterized over an arbitrary cache hierarchy, and our full-system proof is the first machine verification of sequential consistency for a multicore hardware design that includes caches and speculative processors.

Keywords

Hardware Design Label Transition System Speculative Load Program Counter Coherence State 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgments

This work was supported in part by NSF grant CCF-1253229 and in part by the Defense Advanced Research Projects Agency (DARPA) and the United States Air Force, under Contract No. FA8750-11-C-0249. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the Department of Defense or the U.S. Government.

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Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  • Muralidaran Vijayaraghavan
    • 1
  • Adam Chlipala
    • 1
  • Arvind
    • 1
  • Nirav Dave
    • 2
  1. 1.MITCambridgeUSA
  2. 2.SRI InternationalMenlo ParkUSA

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