Advertisement

Technology Mapping for Single Target Gate Based Circuits Using Boolean Functional Decomposition

  • Nabila Abdessaied
  • Mathias Soeken
  • Rolf Drechsler
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9138)

Abstract

Quantum computing offers a promising emerging technology due to the potential theoretical capacity of solving many important problems with exponentially less complexity. Since most of the known quantum algorithms include Boolean components, the design of quantum computers is often conducted by a two-stage approach. In a first step, the Boolean component is realized in reversible logic and then mapped to quantum gates in a second step. This paper describes a new mapping flow for determining quantum gate realizations for single-target gates (ST). Since each ST gate contains a Boolean control function, our method attempts to find a decomposition based on its BDD representation. It consists on breaking large ST gate into smaller ones using additional lines. Experiments show that we obtain smaller realizations when comparing to standard mapping.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Devitt, S.J.: Classical control of large-scale quantum computers. In: Yamashita, S., Minato, S. (eds.) RC 2014. LNCS, vol. 8507, pp. 26–39. Springer, Heidelberg (2014) Google Scholar
  2. 2.
    Nielsen, M., Chuang, I.: Quantum Computation and Quantum Information. Cambridge Univ. Press (2000)Google Scholar
  3. 3.
    Fowler, A.G., Stephens, A.M., Groszkowski, P.: High-threshold universal quantum computation on the surface code. Physical Review A 80, 052312 (2009)CrossRefGoogle Scholar
  4. 4.
    Barenco, A., Bennett, C.H., Cleve, R., DiVinchenzo, D., Margolus, N., Shor, P., Sleator, T., Smolin, J., Weinfurter, H.: Elementary gates for quantum computation. Physical Review A 52, 3457–3467 (1995)CrossRefGoogle Scholar
  5. 5.
    Maslov, D., Dueck, G.W., Miller, D.M.: Toffoli network synthesis with templates. IEEE Trans. on CAD of Integrated Circuits and Systems 24(6), 807–817 (2005)CrossRefGoogle Scholar
  6. 6.
    De Vos, A., Van Rentergem, Y.: Young subgroups for reversible computers. Advances in Mathematics of Communications 2(2), 183–200 (2008)zbMATHMathSciNetCrossRefGoogle Scholar
  7. 7.
    Soeken, M., Tague, L., Dueck, G.W., Drechsler, R.: Ancilla-free synthesis of large reversible functions using binary decision diagrams (2014). CoRR abs/1408.3955Google Scholar
  8. 8.
    Sasao, T.: AND-EXOR expressions and their optimization. In: Sasao, T., (ed.) Logic Synthesis and Optimization. Kluwer Academic Publisher, pp. 287–312 (1993)Google Scholar
  9. 9.
    Ashenhurst, R.L.: The decomposition of switching functions. In: Int’l Symp. on the Theory of Switching, pp. 74–116 (1957)Google Scholar
  10. 10.
    Curtis, H.A.: A new approach to the design of switching circuits. van Nostrand Princeton, NJ (1962)Google Scholar
  11. 11.
    Brayton, R.K.: Factoring logic functions. IBM Journal of Research and Development 31(2), 187–198 (1987)zbMATHMathSciNetCrossRefGoogle Scholar
  12. 12.
    Sasao, T., Matsuura, M.: DECOMPOS: an integrated system for functional decomposition. In: Int’l Workshop on Logic Synthesis, pp. 471–477 (1998)Google Scholar
  13. 13.
    Mishchenko, A., Brayton, R.K., Chatterjee, S.: Boolean factoring and decomposition of logic networks. In: Int’l Conf. on Computer-Aided Design, pp. 38–44 (2008)Google Scholar
  14. 14.
    Mishchenko, A., Steinbach, B., Perkowski, M.A.: An algorithm for bi-decomposition of logic functions. In: Design Automation Conference, pp. 103–108 (2001)Google Scholar
  15. 15.
    Bertacco, V., Damiani, M.: The disjunctive decomposition of logic functions. In: Int’l Conf. on Computer-Aided Design, pp. 78–82 (1997)Google Scholar
  16. 16.
    Yang, C., Ciesielski, M.J.: BDS: a BDD-based logic optimization system. IEEE Trans. on CAD of Integrated Circuits and Systems 21(7), 866–876 (2002)CrossRefGoogle Scholar
  17. 17.
    Abdessaied, N., Soeken, M., Thomsen, M.K., Drechsler, R.: Upper bounds for reversible circuits based on Young subgroups. Information Processing Letters 114(6), 282–286 (2014)zbMATHMathSciNetCrossRefGoogle Scholar
  18. 18.
    Van Rentergem, Y., De Vos, A., Storme, L.: Implementing an arbitrary reversible logic gate. Journal of Physics A: Mathematical and General 38(16), 3555–3577 (2005)zbMATHMathSciNetCrossRefGoogle Scholar
  19. 19.
    Soeken, M., Frehse, S., Wille, R., Drechsler, R.: RevKit: A toolkit for reversible circuit design. Journal of Multiple-Valued Logic & Soft Computing 18(1) (2012). RevKit is available at http://www.revkit.org
  20. 20.
    Vemuri, N., Kalla, P., Tessier, R.: BDD-based logic synthesis for LUT-based FPGAs. ACM Trans. Design Autom. Electr. Syst. 7(4), 501–525 (2002)CrossRefGoogle Scholar
  21. 21.
    Mishchenko, A., Perkowski, M.: Fast heuristic minimization of exclusive-sums-of-products. In: Int’l Workshop on Applications of the Reed-Muller Expansion in Circuit Design, pp. 242–250 (2001)Google Scholar

Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  • Nabila Abdessaied
    • 1
  • Mathias Soeken
    • 1
    • 2
  • Rolf Drechsler
    • 1
    • 2
  1. 1.Cyber-Physical Systems, DFKI GmbHBremenGermany
  2. 2.Institute of Computer ScienceUniversity of BremenBremenGermany

Personalised recommendations