Formal Verification of Industrial Critical Software

Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9128)


In this paper, the challenges for using formal verification based on automatic tools, like model-checkers, in the industrial development process of safety critical systems is discussed. This usage must be integrated into an appropriate process and must allow for independent result-checking.

Our approach is illustrated with a case study from the openETCS ITEA2 research project using the Systerel Smart Solver S3, a modern SAT-based model-checker for equivalence checking and safety properties analysis of SCADE, C or Ada programs.


Equivalence Check Safety Property Proof Obligation High Level Language Generate Test Case 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  1. 1.Systerel, Les portes de l’Arbois, bâtiment AAix-en-Provence CEDEX 3France

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