Static Optimal Scheduling for Synchronous Data Flow Graphs with Model Checking

  • Xue-Yang ZhuEmail author
  • Rongjie Yan
  • Yu-Lei Gu
  • Jian Zhang
  • Wenhui Zhang
  • Guangquan Zhang
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9109)


Synchronous data flow graphs (SDFGs) are widely used to model digital signal processing and streaming media applications. In this paper, we present exact methods for static optimal scheduling and mapping of SDFGs on a heterogenous multiprocessor platform. The optimization criteria we consider are throughput and energy consumption, taking into account the combination of various constraints such as auto-concurrency and buffer sizes. We present a concise and flexible (priced) timed automata semantics of system models, which include an SDFG and a multiprocessor platform, and formulate the optimization goals as temporal logic formulas. The optimization and scheduling problems are then transformed to model checking problems, which are solved by UPPAAL (CORA). Thanks to the exhaustive exploration nature of model checking and the facility of the tools, we obtain two pareto-optimal schedules, one with an optimal throughput and a best energy consumption and another with an optimal energy consumption and a best throughput. The approach is applied to two real applications with different parameters. The case studies show that our approach can deal with moderate models within reasonable execution time and reveal the impacts of different constraints on optimization goals.


Data Flow Graphs Throughput Energy Consumption Multi-constraint Timed Automata UPPAAL 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Abdeddaïm, Y., Asarin, E., Maler, O., et al.: Scheduling with timed automata. Theor. Comput. Sci. 354(2), 272–300 (2006)CrossRefzbMATHGoogle Scholar
  2. 2.
    Adé, M., Lauwereins, R., Peperstraete, J.: Data memory minimisation for synchronous data flow graphs emulated on DSP-FPGA targets. In: Proc. of the 34th Ann. Design Automation Conf (DAC), pp. 64–69 (1997)Google Scholar
  3. 3.
    Alur, R., Dill, D.L.: A theory of timed automata. Theor. Comput. Sci. 126(2), 183–235 (1994)CrossRefzbMATHMathSciNetGoogle Scholar
  4. 4.
    Behrmann, G., Larsen, K.G., Rasmussen, J.I.: Priced timed automata: Algorithms and applications. In: de Boer, F.S., Bonsangue, M.M., Graf, S., de Roever, W.-P. (eds.) FMCO 2004. LNCS, vol. 3657, pp. 162–182. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  5. 5.
    Bouyer, P., Fahrenberg, U., Larsen, K.G., Markey, N.: Quantitative analysis of real-time systems using priced timed automata. Comm. of the ACM 54(9), 78–87 (2011)CrossRefGoogle Scholar
  6. 6.
    Cimatti, A., Clarke, E., Giunchiglia, F., Roveri, M.: NuSMV: a new symbolic model checker. International Journal on Software Tools for Technology Transfer 2(4), 410–425 (2000)CrossRefzbMATHGoogle Scholar
  7. 7.
    Fakih, M., Grüttner, K., Fränzle, M., Rettberg, A.: Towards performance analysis of SDFGs mapped to shared-bus architectures using model-checking. In: Proc. of the Conference on Design, Automation and Test in Europe, pp. 1167–1172 (2013)Google Scholar
  8. 8.
    Fersman, E., Mokrushin, L., Pettersson, P., Yi, W.: Schedulability analysis of fixed-priority systems using timed automata. Theor. Comput. Sci. 354(2), 301 (2006)CrossRefzbMATHMathSciNetGoogle Scholar
  9. 9.
    Geilen, M., Basten, T., Stuijk, S.: Minimising buffer requirements of synchronous dataflow graphs with model checking. In: Proc. of the 42nd Annu. Design Automation Conf. (DAC) (2005)Google Scholar
  10. 10.
    Gu, Z., Yuan, M., Guan, N., Lv, M., He, X., Deng, Q., Yu, G.: Static scheduling and software synthesis for dataflow graphs with symbolic model-checking. In: Proc. of 28th International Real-Time Systems Symposium (RTSS), pp. 353–364 (2007)Google Scholar
  11. 11.
    Harbour, M.G., Klein, M.H., Lehoczky, J.P.: Timing analysis for fixed-priority scheduling of hard real-time systems. IEEE Trans. on Soft. Eng. 20(1), 13–28 (1994)CrossRefGoogle Scholar
  12. 12.
    Hartel, P.H., Ruys, T.C., Geilen, M.C.: Scheduling optimisations for SPIN to minimise buffer requirements in synchronous data flow. In: Proc of the International Conference on Formal Methods in Computer-Aided Design, p. 21 (2008)Google Scholar
  13. 13.
    Hirzel, M., Soulé, R., Schneider, S., Gedik, B., Grimm, R.: A catalog of stream processing optimizations. ACM Comput. Surv. 46(4), 46:1–46:34 (2014)Google Scholar
  14. 14.
    Holzmann, G.J.: The model checker SPIN. IEEE Transactions on Software Engineering 23(5), 279–295 (1997)CrossRefMathSciNetGoogle Scholar
  15. 15.
    Larsen, K.G., Pettersson, P., Yi, W.: UPPAAL in a nutshell. International Journal on Software Tools for Technology Transfer (STTT) 1(1), 134–152 (1997)CrossRefzbMATHGoogle Scholar
  16. 16.
    Lee, E., Messerschmitt, D.: Static scheduling of synchronous data flow programs for digital signal processing. IEEE Trans. Comput. 36(1), 24–35 (1987)CrossRefzbMATHGoogle Scholar
  17. 17.
    Madsen, J., Hansen, M.R., Knudsen, K.S., Nielsen, J.E., Brekling, A.W.: System-level verification of multi-core embedded systems using timed-automata. In: Proc. of the 17th World Congress International Federation of Automatic Control, Seoul, Korea, pp. 9302–9307 (2008)Google Scholar
  18. 18.
    Malik, A., Gregg, D.: Orchestrating stream graphs using model checking. ACM Trans. Archit. Code Optim. 10(3), 19:1–19:25 (2013)Google Scholar
  19. 19.
    Parhi, K.K., Messerschmitt, D.G.: Static rate-optimal scheduling of iterative data-flow programs via optimum unfolding. IEEE Trans. Comput. 40(2), 178–195 (1991)CrossRefGoogle Scholar
  20. 20.
    Singh, A.K., Shafique, M., Kumar, A., Henkel, J.: Mapping on multi/many-core systems: Survey of current and emerging trends. In: Proc. of the 50th Ann. Design Automation Conf. (DAC), p. 1 (2013)Google Scholar
  21. 21.
    Sriram, S., Bhattacharyya, S.S.: Embedded multiprocessors: scheduling and synchronization. CRC Press (2009)Google Scholar
  22. 22.
    Stuijk, S., Geilen, M., Basten, T.: Throughput-buffering trade-off exploration for cyclo-static and synchronous dataflow graphs. IEEE Trans. Comput. 57(10), 1331–1345 (2008)CrossRefMathSciNetGoogle Scholar
  23. 23.
    Theelen, B., Katoen, J.P., Wu, H.: Model checking of scenario-aware dataflow with CADP. In: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 653–658 (2012)Google Scholar
  24. 24.
    Zhu, X.-Y., Geilen, M., Basten, T., Stuijk, S.: Static rate-optimal scheduling of multirate DSP algorithms via retiming and unfolding. In: Proc. of the 18th Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 109–118 (2012)Google Scholar
  25. 25.
    Zivojnovic, V., Ritz, S., Meyr, H.: Optimizing DSP programs using the multirate retiming transformation. Proc. EUSIPCO Signal Process. VII, Theories Applicat. (1994)Google Scholar

Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  • Xue-Yang Zhu
    • 1
    Email author
  • Rongjie Yan
    • 1
  • Yu-Lei Gu
    • 1
    • 2
  • Jian Zhang
    • 1
  • Wenhui Zhang
    • 1
  • Guangquan Zhang
    • 2
  1. 1.State Key Laboratory of Computer ScienceInstitute of Software, Chinese Academy of SciencesBeijingChina
  2. 2.School of Computer Science and TechnologySoochow UniversitySuzhouChina

Personalised recommendations