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Modeling Stencil Computations on Modern HPC Architectures

  • Raúl de la CruzEmail author
  • Mauricio Araya-Polo
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8966)

Abstract

Stencil computations are widely used for solving Partial Differential Equations (PDEs) explicitly by Finite Difference schemes. The stencil solver alone -depending on the governing equation- can represent up to 90 % of the overall elapsed time, of which moving data back and forth from memory to CPU is a major concern. Therefore, the development and analysis of source code modifications that can effectively use the memory hierarchy of modern architectures is crucial. Performance models help expose bottlenecks and predict suitable tuning parameters in order to boost stencil performance on any given platform. To achieve that, the following two considerations need to be accurately modeled: first, modern architectures, such as Intel Xeon Phi, sport multi- or many-core processors with shared multi-level caches featuring one or several prefetching engines. Second, algorithmic optimizations, such as spatial blocking or Semi-stencil, have complex behaviors that follow the intricacy of the above described modern architectures. In this work, a previously published performance model is extended to effectively capture these architectural and algorithmic characteristics. The extended model results show an accuracy error ranging from 5–15 %.

Keywords

Stencil computation FD Modeling HPC Prefetching Spatial blocking Semi-stencil Multi-core Intel Xeon Phi 

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Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  1. 1.CASE DepartmentBarcelona Supercomputing CenterBarcelonaSpain
  2. 2.Shell International Exploration and Production Inc.HoustonUSA

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